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[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc] #117605

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Merged
merged 2 commits into from
Nov 25, 2024
Merged

[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc] #117605

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[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc]
preames Nov 22, 2024
762bb74
clang-format
preames Nov 25, 2024
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43 changes: 9 additions & 34 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -498,36 +498,6 @@ getPushOrLibCallsSavedInfo(const MachineFunction &MF,
return PushOrLibCallsCSI;
}

void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, int64_t Amount,
MachineInstr::MIFlag Flag) const {
assert(Amount != 0 && "Did not need to adjust stack pointer for RVV.");

// Optimize compile time offset case
StackOffset Offset = StackOffset::getScalable(Amount);
if (auto VLEN = STI.getRealVLen()) {
// 1. Multiply the number of v-slots by the (constant) length of register
const int64_t VLENB = *VLEN / 8;
assert(Amount % 8 == 0 &&
"Reserve the stack by the multiple of one vector size.");
const int64_t NumOfVReg = Amount / 8;
const int64_t FixedOffset = NumOfVReg * VLENB;
if (!isInt<32>(FixedOffset)) {
report_fatal_error(
"Frame size outside of the signed 32-bit range not supported");
}
Offset = StackOffset::getFixed(FixedOffset);
}

const RISCVRegisterInfo &RI = *STI.getRegisterInfo();
// We must keep the stack pointer aligned through any intermediate
// updates.
RI.adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset,
Flag, getStackAlign());
}

static void appendScalableVectorExpression(const TargetRegisterInfo &TRI,
SmallVectorImpl<char> &Expr,
int FixedOffset, int ScalableOffset,
Expand Down Expand Up @@ -793,8 +763,12 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
}

if (RVVStackSize) {
adjustStackForRVV(MF, MBB, MBBI, DL, -RVVStackSize,
MachineInstr::FrameSetup);
// We must keep the stack pointer aligned through any intermediate
// updates.
RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
StackOffset::getScalable(-RVVStackSize),
MachineInstr::FrameSetup, getStackAlign());

if (!hasFP(MF)) {
// Emit .cfi_def_cfa_expression "sp + StackSize + RVVStackSize * vlenb".
unsigned CFIIndex = MF.addFrameInst(createDefCFAExpression(
Expand Down Expand Up @@ -919,8 +893,9 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
// If RestoreSPFromFP the stack pointer will be restored using the frame
// pointer value.
if (!RestoreSPFromFP)
adjustStackForRVV(MF, MBB, LastFrameDestroy, DL, RVVStackSize,
MachineInstr::FrameDestroy);
RI->adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg,
StackOffset::getScalable(RVVStackSize),
MachineInstr::FrameDestroy, getStackAlign());

if (!hasFP(MF)) {
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
Expand Down
3 changes: 0 additions & 3 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -85,9 +85,6 @@ class RISCVFrameLowering : public TargetFrameLowering {

private:
void determineFrameLayout(MachineFunction &MF) const;
void adjustStackForRVV(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
int64_t Amount, MachineInstr::MIFlag Flag) const;
void emitCalleeSavedRVVPrologCFI(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
bool HasFP) const;
Expand Down
30 changes: 17 additions & 13 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -184,6 +184,23 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
const RISCVInstrInfo *TII = ST.getInstrInfo();

// Optimize compile time offset case
if (Offset.getScalable()) {
if (auto VLEN = ST.getRealVLen()) {
// 1. Multiply the number of v-slots by the (constant) length of register
const int64_t VLENB = *VLEN / 8;
assert(Offset.getScalable() % (RISCV::RVVBitsPerBlock / 8) == 0 &&
"Reserve the stack by the multiple of one vector size.");
const int64_t NumOfVReg = Offset.getScalable() / 8;
const int64_t FixedOffset = NumOfVReg * VLENB;
if (!isInt<32>(FixedOffset)) {
report_fatal_error(
"Frame size outside of the signed 32-bit range not supported");
}
Offset = StackOffset::getFixed(FixedOffset + Offset.getFixed());
}
}

bool KillSrcReg = false;

if (Offset.getScalable()) {
Expand Down Expand Up @@ -467,19 +484,6 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
if (!IsRVVSpill)
Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());

if (Offset.getScalable() &&
ST.getRealMinVLen() == ST.getRealMaxVLen()) {
// For an exact VLEN value, scalable offsets become constant and thus
// can be converted entirely into fixed offsets.
int64_t FixedValue = Offset.getFixed();
int64_t ScalableValue = Offset.getScalable();
assert(ScalableValue % 8 == 0 &&
"Scalable offset is not a multiple of a single vector size.");
int64_t NumOfVReg = ScalableValue / 8;
int64_t VLENB = ST.getRealMinVLen() / 8;
Offset = StackOffset::getFixed(FixedValue + NumOfVReg * VLENB);
}

if (!isInt<32>(Offset.getFixed())) {
report_fatal_error(
"Frame offsets outside of the signed 32-bit range not supported");
Expand Down
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