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2 changes: 2 additions & 0 deletions llvm/test/MachineVerifier/RISCV/lit.local.cfg
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
if not "RISCV" in config.root.targets:
config.unsupported = True
1 change: 0 additions & 1 deletion llvm/test/MachineVerifier/RISCV/subreg-liveness.mir
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=none %s -o - | FileCheck %s
# REQUIRES: riscv64-registered-target

# During the MachineVerifier, it assumes that used registers have been defined
# In this test case, while $v12_v13_v14_v15_v16 covers $v14_v15,
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