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[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened #118269

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Merged
topperc merged 1 commit into from
Dec 2, 2024
Merged

[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened #118269

topperc merged 1 commit into from
Dec 2, 2024

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@topperc topperc commented Dec 2, 2024

This avoids an unnecessary sext.w before the libcall.

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[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes…
166ee7d 
…_FP_TO_XINT if the FP type needs to be softened

This avoids an unnecessary sext.w before the libcall.
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@llvmbot llvmbot added the llvm:SelectionDAG SelectionDAGISel as well label Dec 2, 2024
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llvmbot commented Dec 2, 2024

@llvm/pr-subscribers-llvm-selectiondag

Author: Craig Topper (topperc)

Changes

This avoids an unnecessary sext.w before the libcall.

Full diff: https://github.com/llvm/llvm-project/pull/118269.diff

5 Files Affected:

  • (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (+10-3)
  • (modified) llvm/test/CodeGen/RISCV/rv64-float-convert-strict.ll (+20-54)
  • (modified) llvm/test/CodeGen/RISCV/rv64-float-convert.ll (+27-65)
  • (modified) llvm/test/CodeGen/RISCV/rv64-half-convert-strict.ll (-2)
  • (modified) llvm/test/CodeGen/RISCV/rv64-half-convert.ll (+8-10)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 7b9f544a5f9a48..493abfde148c65 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -3995,11 +3995,18 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT(SDNode *N, SDValue &Lo,
     Op = fpExtendHelper(Op, Chain, IsStrict, MVT::f32, dl, DAG);
   }
 
-  RTLIB::Libcall LC = IsSigned ? RTLIB::getFPTOSINT(Op.getValueType(), VT)
-                               : RTLIB::getFPTOUINT(Op.getValueType(), VT);
+  // NOTE: We need a variable that lives across makeLibCall so
+  // CallOptions.setTypeListBeforeSoften can save a reference to it.
+  EVT OpVT = Op.getValueType();
+
+  RTLIB::Libcall LC =
+      IsSigned ? RTLIB::getFPTOSINT(OpVT, VT) : RTLIB::getFPTOUINT(OpVT, VT);
   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-xint conversion!");
   TargetLowering::MakeLibCallOptions CallOptions;
-  CallOptions.setSExt(true);
+  if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftenFloat)
+    CallOptions.setTypeListBeforeSoften(OpVT, VT);
+  else
+    CallOptions.setSExt(true);
   std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
                                                     CallOptions, dl, Chain);
   SplitInteger(Tmp.first, Lo, Hi);
diff --git a/llvm/test/CodeGen/RISCV/rv64-float-convert-strict.ll b/llvm/test/CodeGen/RISCV/rv64-float-convert-strict.ll
index 86d1801928ea1d..7065a7120175d6 100644
--- a/llvm/test/CodeGen/RISCV/rv64-float-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-float-convert-strict.ll
@@ -7,65 +7,27 @@
 ; RUN:   -disable-strictnode-mutation | FileCheck %s -check-prefixes=CHECK,RV64IFINX
 
 define i128 @fptosi_f32_to_i128(float %a) nounwind strictfp {
-; RV64I-LABEL: fptosi_f32_to_i128:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sext.w a0, a0
-; RV64I-NEXT:    call __fixsfti
-; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    ret
-;
-; RV64IF-LABEL: fptosi_f32_to_i128:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    addi sp, sp, -16
-; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IF-NEXT:    call __fixsfti
-; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IF-NEXT:    addi sp, sp, 16
-; RV64IF-NEXT:    ret
-;
-; RV64IFINX-LABEL: fptosi_f32_to_i128:
-; RV64IFINX:       # %bb.0:
-; RV64IFINX-NEXT:    addi sp, sp, -16
-; RV64IFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IFINX-NEXT:    call __fixsfti
-; RV64IFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IFINX-NEXT:    addi sp, sp, 16
-; RV64IFINX-NEXT:    ret
+; CHECK-LABEL: fptosi_f32_to_i128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    call __fixsfti
+; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %1 = call i128 @llvm.experimental.constrained.fptosi.i128.f32(float %a, metadata !"fpexcept.strict")
   ret i128 %1
 }
 
 define i128 @fptoui_f32_to_i128(float %a) nounwind strictfp {
-; RV64I-LABEL: fptoui_f32_to_i128:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sext.w a0, a0
-; RV64I-NEXT:    call __fixunssfti
-; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    ret
-;
-; RV64IF-LABEL: fptoui_f32_to_i128:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    addi sp, sp, -16
-; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IF-NEXT:    call __fixunssfti
-; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IF-NEXT:    addi sp, sp, 16
-; RV64IF-NEXT:    ret
-;
-; RV64IFINX-LABEL: fptoui_f32_to_i128:
-; RV64IFINX:       # %bb.0:
-; RV64IFINX-NEXT:    addi sp, sp, -16
-; RV64IFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IFINX-NEXT:    call __fixunssfti
-; RV64IFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IFINX-NEXT:    addi sp, sp, 16
-; RV64IFINX-NEXT:    ret
+; CHECK-LABEL: fptoui_f32_to_i128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    call __fixunssfti
+; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %1 = call i128 @llvm.experimental.constrained.fptoui.i128.f32(float %a, metadata !"fpexcept.strict")
   ret i128 %1
 }
@@ -95,3 +57,7 @@ define float @uitofp_i128_to_f32(i128 %a) nounwind strictfp {
   %1 = call float @llvm.experimental.constrained.uitofp.f32.i128(i128 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret float %1
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV64I: {{.*}}
+; RV64IF: {{.*}}
+; RV64IFINX: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rv64-float-convert.ll b/llvm/test/CodeGen/RISCV/rv64-float-convert.ll
index 0cdd92fbaf916b..e387586cd46c27 100644
--- a/llvm/test/CodeGen/RISCV/rv64-float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-float-convert.ll
@@ -7,65 +7,27 @@
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64IZFINX
 
 define i128 @fptosi_f32_to_i128(float %a) nounwind {
-; RV64I-LABEL: fptosi_f32_to_i128:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sext.w a0, a0
-; RV64I-NEXT:    call __fixsfti
-; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    ret
-;
-; RV64IF-LABEL: fptosi_f32_to_i128:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    addi sp, sp, -16
-; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IF-NEXT:    call __fixsfti
-; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IF-NEXT:    addi sp, sp, 16
-; RV64IF-NEXT:    ret
-;
-; RV64IZFINX-LABEL: fptosi_f32_to_i128:
-; RV64IZFINX:       # %bb.0:
-; RV64IZFINX-NEXT:    addi sp, sp, -16
-; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFINX-NEXT:    call __fixsfti
-; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFINX-NEXT:    addi sp, sp, 16
-; RV64IZFINX-NEXT:    ret
+; CHECK-LABEL: fptosi_f32_to_i128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    call __fixsfti
+; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %1 = fptosi float %a to i128
   ret i128 %1
 }
 
 define i128 @fptoui_f32_to_i128(float %a) nounwind {
-; RV64I-LABEL: fptoui_f32_to_i128:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sext.w a0, a0
-; RV64I-NEXT:    call __fixunssfti
-; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    ret
-;
-; RV64IF-LABEL: fptoui_f32_to_i128:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    addi sp, sp, -16
-; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IF-NEXT:    call __fixunssfti
-; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IF-NEXT:    addi sp, sp, 16
-; RV64IF-NEXT:    ret
-;
-; RV64IZFINX-LABEL: fptoui_f32_to_i128:
-; RV64IZFINX:       # %bb.0:
-; RV64IZFINX-NEXT:    addi sp, sp, -16
-; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFINX-NEXT:    call __fixunssfti
-; RV64IZFINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFINX-NEXT:    addi sp, sp, 16
-; RV64IZFINX-NEXT:    ret
+; CHECK-LABEL: fptoui_f32_to_i128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    call __fixunssfti
+; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %1 = fptoui float %a to i128
   ret i128 %1
 }
@@ -107,38 +69,38 @@ define i128 @fptosi_sat_f32_to_i128(float %a) nounwind {
 ; RV64I-NEXT:    sd s3, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s4, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s5, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    mv s0, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui a1, 1044480
 ; RV64I-NEXT:    call __gesf2
-; RV64I-NEXT:    mv s1, a0
-; RV64I-NEXT:    sext.w a0, s0
-; RV64I-NEXT:    call __fixsfti
 ; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    call __fixsfti
+; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    mv s3, a1
 ; RV64I-NEXT:    li s5, -1
-; RV64I-NEXT:    bgez s1, .LBB4_2
+; RV64I-NEXT:    bgez s2, .LBB4_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    slli s3, s5, 63
 ; RV64I-NEXT:  .LBB4_2:
 ; RV64I-NEXT:    lui a1, 520192
 ; RV64I-NEXT:    addiw a1, a1, -1
-; RV64I-NEXT:    mv a0, s0
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    call __gtsf2
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    blez a0, .LBB4_4
 ; RV64I-NEXT:  # %bb.3:
 ; RV64I-NEXT:    srli s3, s5, 1
 ; RV64I-NEXT:  .LBB4_4:
-; RV64I-NEXT:    mv a0, s0
-; RV64I-NEXT:    mv a1, s0
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s1
 ; RV64I-NEXT:    call __unordsf2
 ; RV64I-NEXT:    snez a0, a0
-; RV64I-NEXT:    slti a1, s1, 0
+; RV64I-NEXT:    slti a1, s2, 0
 ; RV64I-NEXT:    sgtz a2, s4
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    addi a3, a1, -1
 ; RV64I-NEXT:    and a1, a0, s3
-; RV64I-NEXT:    and a3, a3, s2
+; RV64I-NEXT:    and a3, a3, s0
 ; RV64I-NEXT:    neg a2, a2
 ; RV64I-NEXT:    or a2, a2, a3
 ; RV64I-NEXT:    and a0, a0, a2
@@ -249,7 +211,7 @@ define i128 @fptoui_sat_f32_to_i128(float %a) nounwind {
 ; RV64I-NEXT:    call __gesf2
 ; RV64I-NEXT:    slti a0, a0, 0
 ; RV64I-NEXT:    addi s2, a0, -1
-; RV64I-NEXT:    sext.w a0, s0
+; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixunssfti
 ; RV64I-NEXT:    and a0, s2, a0
 ; RV64I-NEXT:    and a1, s2, a1
diff --git a/llvm/test/CodeGen/RISCV/rv64-half-convert-strict.ll b/llvm/test/CodeGen/RISCV/rv64-half-convert-strict.ll
index e9554bce1d5012..67aa4ca4c94091 100644
--- a/llvm/test/CodeGen/RISCV/rv64-half-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-half-convert-strict.ll
@@ -15,7 +15,6 @@ define i128 @fptosi_f16_to_i128(half %a) nounwind strictfp {
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __extendhfsf2
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    call __fixsfti
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
@@ -48,7 +47,6 @@ define i128 @fptoui_f16_to_i128(half %a) nounwind strictfp {
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __extendhfsf2
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    call __fixunssfti
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rv64-half-convert.ll b/llvm/test/CodeGen/RISCV/rv64-half-convert.ll
index a717c6c71f2ec0..ea582ac258b710 100644
--- a/llvm/test/CodeGen/RISCV/rv64-half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-half-convert.ll
@@ -76,7 +76,6 @@ define i128 @fptosi_f16_to_i128(half %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __extendhfsf2
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    call __fixsfti
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
@@ -109,7 +108,6 @@ define i128 @fptoui_f16_to_i128(half %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __extendhfsf2
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    call __fixunssfti
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
@@ -148,13 +146,13 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
 ; RV64I-NEXT:    sd s4, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s5, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __extendhfsf2
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    lui a1, 1044480
 ; RV64I-NEXT:    call __gesf2
 ; RV64I-NEXT:    mv s0, a0
-; RV64I-NEXT:    sext.w a0, s1
+; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __fixsfti
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    mv s3, a1
 ; RV64I-NEXT:    li s5, -1
 ; RV64I-NEXT:    bgez s0, .LBB4_2
@@ -163,15 +161,15 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
 ; RV64I-NEXT:  .LBB4_2:
 ; RV64I-NEXT:    lui a1, 520192
 ; RV64I-NEXT:    addiw a1, a1, -1
-; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtsf2
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    blez a0, .LBB4_4
 ; RV64I-NEXT:  # %bb.3:
 ; RV64I-NEXT:    srli s3, s5, 1
 ; RV64I-NEXT:  .LBB4_4:
-; RV64I-NEXT:    mv a0, s1
-; RV64I-NEXT:    mv a1, s1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    call __unordsf2
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    sgtz a1, s4
@@ -180,7 +178,7 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
 ; RV64I-NEXT:    neg a3, a1
 ; RV64I-NEXT:    addi a2, a2, -1
 ; RV64I-NEXT:    and a1, a0, s3
-; RV64I-NEXT:    and a2, a2, s2
+; RV64I-NEXT:    and a2, a2, s1
 ; RV64I-NEXT:    or a2, a3, a2
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
@@ -292,7 +290,7 @@ define i128 @fptoui_sat_f16_to_i128(half %a) nounwind {
 ; RV64I-NEXT:    call __gesf2
 ; RV64I-NEXT:    slti a0, a0, 0
 ; RV64I-NEXT:    addi s2, a0, -1
-; RV64I-NEXT:    sext.w a0, s0
+; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixunssfti
 ; RV64I-NEXT:    and a0, s2, a0
 ; RV64I-NEXT:    and a1, s2, a1

lenary
lenary approved these changes Dec 2, 2024
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LGTM

@topperc topperc merged commit 7318654 into llvm:main Dec 2, 2024
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@topperc topperc deleted the pr/libcall-sext branch December 2, 2024 17:06
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