[AMDGPU] Support s_endpgm_ordered_ps_done on GFX11 #119230
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Support assembly/disassembly of this instruction for compatibility with SP3, even though it has no use in GFX11. It is fully removed in GFX12.
Member
|
@llvm/pr-subscribers-backend-amdgpu Author: Jay Foad (jayfoad) ChangesSupport assembly/disassembly of this instruction for compatibility with Full diff: https://github.com/llvm/llvm-project/pull/119230.diff 6 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index ebe6f0965deb97..7ad6720b8001af 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -2136,6 +2136,11 @@ def isGFX9GFX10 :
"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureGFX11Insts))>;
+def isGFX9GFX10GFX11 :
+ Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9 &&"
+ "Subtarget->getGeneration() < AMDGPUSubtarget::GFX12">,
+ AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureGFX12Insts))>;
+
def isGFX8GFX9GFX10 :
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
"Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index c0697c80b23f98..849f8a0f183cfc 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1512,12 +1512,12 @@ def S_ENDPGM_SAVED : SOPP_Pseudo<"s_endpgm_saved", (ins)> {
let isReturn = 1;
}
-let SubtargetPredicate = isGFX9GFX10 in {
+let SubtargetPredicate = isGFX9GFX10GFX11 in {
let isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1 in {
def S_ENDPGM_ORDERED_PS_DONE :
SOPP_Pseudo<"s_endpgm_ordered_ps_done", (ins)>;
} // End isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1
-} // End SubtargetPredicate = isGFX9GFX10
+} // End SubtargetPredicate = isGFX9GFX10GFX11
let SubtargetPredicate = isGFX10Plus in {
let isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1 in {
@@ -2661,6 +2661,7 @@ defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_Real_With_Relaxation_gfx11<0x029>;
defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx11<0x02a>;
defm S_ENDPGM : SOPP_Real_32_gfx11_gfx12<0x030>;
defm S_ENDPGM_SAVED : SOPP_Real_32_gfx11_gfx12<0x031>;
+defm S_ENDPGM_ORDERED_PS_DONE : SOPP_Real_32_gfx11<0x032>;
defm S_WAKEUP : SOPP_Real_32_gfx11_gfx12<0x034>;
defm S_SETPRIO : SOPP_Real_32_gfx11_gfx12<0x035>;
defm S_SENDMSG : SOPP_Real_32_gfx11_gfx12<0x036>;
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
index 8d7fed65a77636..c3b97e8de6c452 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
@@ -430,3 +430,6 @@ s_wait_event 0x3141
s_wait_event 0xc1d1
// GFX11: s_wait_event 0xc1d1 ; encoding: [0xd1,0xc1,0x8b,0xbf]
+
+s_endpgm_ordered_ps_done
+// GFX11: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0xb2,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx12_err.s b/llvm/test/MC/AMDGPU/gfx12_err.s
index d55b86b54ec7d8..b07e160454ef7c 100644
--- a/llvm/test/MC/AMDGPU/gfx12_err.s
+++ b/llvm/test/MC/AMDGPU/gfx12_err.s
@@ -113,3 +113,6 @@ s_prefetch_inst s[14:15], 0xffffff, m0, 7
// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 24-bit signed offset
// GFX12-ERR: s_prefetch_inst s[14:15], 0xffffff, m0, 7
// GFX12-ERR: ^
+
+s_endpgm_ordered_ps_done
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/sopk.s b/llvm/test/MC/AMDGPU/sopk.s
index 59c93fefcfaa23..1a21dae92e5dd8 100644
--- a/llvm/test/MC/AMDGPU/sopk.s
+++ b/llvm/test/MC/AMDGPU/sopk.s
@@ -478,7 +478,7 @@ s_endpgm_ordered_ps_done
// GFX9: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
// NOSICIVI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
// GFX10: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
-// NOGFX11: :[[@LINE-4]]:{{[0-9]+}}: error: instruction not supported on this GPU
+// GFX11: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0xb2,0xbf]
s_call_b64 null, 12609
// GFX10: s_call_b64 null, 12609 ; encoding: [0x41,0x31,0x7d,0xbb]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt
index 51604da454d16f..c21f2fcc375d67 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt
@@ -294,3 +294,6 @@
# GFX11: s_wait_event 0xc1d1 ; encoding: [0xd1,0xc1,0x8b,0xbf]
0xd1,0xc1,0x8b,0xbf
+
+# GFX11: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0xb2,0xbf]
+0x00,0x00,0xb2,0xbf
|
Member
|
@llvm/pr-subscribers-mc Author: Jay Foad (jayfoad) ChangesSupport assembly/disassembly of this instruction for compatibility with Full diff: https://github.com/llvm/llvm-project/pull/119230.diff 6 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index ebe6f0965deb97..7ad6720b8001af 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -2136,6 +2136,11 @@ def isGFX9GFX10 :
"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureGFX11Insts))>;
+def isGFX9GFX10GFX11 :
+ Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9 &&"
+ "Subtarget->getGeneration() < AMDGPUSubtarget::GFX12">,
+ AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureGFX12Insts))>;
+
def isGFX8GFX9GFX10 :
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
"Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index c0697c80b23f98..849f8a0f183cfc 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1512,12 +1512,12 @@ def S_ENDPGM_SAVED : SOPP_Pseudo<"s_endpgm_saved", (ins)> {
let isReturn = 1;
}
-let SubtargetPredicate = isGFX9GFX10 in {
+let SubtargetPredicate = isGFX9GFX10GFX11 in {
let isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1 in {
def S_ENDPGM_ORDERED_PS_DONE :
SOPP_Pseudo<"s_endpgm_ordered_ps_done", (ins)>;
} // End isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1
-} // End SubtargetPredicate = isGFX9GFX10
+} // End SubtargetPredicate = isGFX9GFX10GFX11
let SubtargetPredicate = isGFX10Plus in {
let isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1 in {
@@ -2661,6 +2661,7 @@ defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_Real_With_Relaxation_gfx11<0x029>;
defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx11<0x02a>;
defm S_ENDPGM : SOPP_Real_32_gfx11_gfx12<0x030>;
defm S_ENDPGM_SAVED : SOPP_Real_32_gfx11_gfx12<0x031>;
+defm S_ENDPGM_ORDERED_PS_DONE : SOPP_Real_32_gfx11<0x032>;
defm S_WAKEUP : SOPP_Real_32_gfx11_gfx12<0x034>;
defm S_SETPRIO : SOPP_Real_32_gfx11_gfx12<0x035>;
defm S_SENDMSG : SOPP_Real_32_gfx11_gfx12<0x036>;
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
index 8d7fed65a77636..c3b97e8de6c452 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
@@ -430,3 +430,6 @@ s_wait_event 0x3141
s_wait_event 0xc1d1
// GFX11: s_wait_event 0xc1d1 ; encoding: [0xd1,0xc1,0x8b,0xbf]
+
+s_endpgm_ordered_ps_done
+// GFX11: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0xb2,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx12_err.s b/llvm/test/MC/AMDGPU/gfx12_err.s
index d55b86b54ec7d8..b07e160454ef7c 100644
--- a/llvm/test/MC/AMDGPU/gfx12_err.s
+++ b/llvm/test/MC/AMDGPU/gfx12_err.s
@@ -113,3 +113,6 @@ s_prefetch_inst s[14:15], 0xffffff, m0, 7
// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 24-bit signed offset
// GFX12-ERR: s_prefetch_inst s[14:15], 0xffffff, m0, 7
// GFX12-ERR: ^
+
+s_endpgm_ordered_ps_done
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/sopk.s b/llvm/test/MC/AMDGPU/sopk.s
index 59c93fefcfaa23..1a21dae92e5dd8 100644
--- a/llvm/test/MC/AMDGPU/sopk.s
+++ b/llvm/test/MC/AMDGPU/sopk.s
@@ -478,7 +478,7 @@ s_endpgm_ordered_ps_done
// GFX9: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
// NOSICIVI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
// GFX10: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
-// NOGFX11: :[[@LINE-4]]:{{[0-9]+}}: error: instruction not supported on this GPU
+// GFX11: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0xb2,0xbf]
s_call_b64 null, 12609
// GFX10: s_call_b64 null, 12609 ; encoding: [0x41,0x31,0x7d,0xbb]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt
index 51604da454d16f..c21f2fcc375d67 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt
@@ -294,3 +294,6 @@
# GFX11: s_wait_event 0xc1d1 ; encoding: [0xd1,0xc1,0x8b,0xbf]
0xd1,0xc1,0x8b,0xbf
+
+# GFX11: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0xb2,0xbf]
+0x00,0x00,0xb2,0xbf
|
arsenm
approved these changes
Dec 11, 2024
| "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">, | ||
| AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureGFX11Insts))>; | ||
|
|
||
| def isGFX9GFX10GFX11 : |
Contributor
There was a problem hiding this comment.
I really hate this style of predicate. We ought to add subtarget features for everything
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
3 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Support assembly/disassembly of this instruction for compatibility with
SP3, even though it has no use in GFX11. It is fully removed in GFX12.