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[AMDGPU][True16][MC] test update for v_mul_f16 in true16 #119314

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Merged
broxigarchen merged 1 commit into from
Dec 17, 2024
Merged

[AMDGPU][True16][MC] test update for v_mul_f16 in true16 #119314

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3 changes: 1 addition & 2 deletions llvm/lib/Target/AMDGPU/VOP2Instructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1822,8 +1822,7 @@ defm V_ADD_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x032, "v
defm V_SUB_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x033, "v_sub_f16">;
defm V_SUBREV_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
defm V_SUBREV_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
defm V_MUL_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">;
defm V_MUL_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">;
defm V_MUL_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x035, "v_mul_f16">;
defm V_FMAC_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x036, "v_fmac_f16">;
defm V_LDEXP_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x03b, "v_ldexp_f16">;
defm V_LDEXP_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x03b, "v_ldexp_f16">;
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75 changes: 45 additions & 30 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
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Expand Up @@ -1582,50 +1582,65 @@ v_mul_dx9_zero_f32 v5, src_scc, v2
v_mul_dx9_zero_f32 v255, 0xaf123456, v255
// GFX11: v_mul_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf]

v_mul_f16 v5, v1, v2
// GFX11: v_mul_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6a]
v_mul_f16 v5.l, v1.l, v2.l
// GFX11: v_mul_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x6a]

v_mul_f16 v5, v127, v2
// GFX11: v_mul_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x6a]
v_mul_f16 v5.l, v127.l, v2.l
// GFX11: v_mul_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x6a]

v_mul_f16 v5, s1, v2
// GFX11: v_mul_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x6a]
v_mul_f16 v5.l, s1, v2.l
// GFX11: v_mul_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x6a]

v_mul_f16 v5, s105, v2
// GFX11: v_mul_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x6a]
v_mul_f16 v5.l, s105, v2.l
// GFX11: v_mul_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x6a]

v_mul_f16 v5, vcc_lo, v2
// GFX11: v_mul_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x6a]
v_mul_f16 v5.l, vcc_lo, v2.l
// GFX11: v_mul_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x6a]

v_mul_f16 v5, vcc_hi, v2
// GFX11: v_mul_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x6a]
v_mul_f16 v5.l, vcc_hi, v2.l
// GFX11: v_mul_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x6a]

v_mul_f16 v5, ttmp15, v2
// GFX11: v_mul_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x6a]
v_mul_f16 v5.l, ttmp15, v2.l
// GFX11: v_mul_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x6a]

v_mul_f16 v5, m0, v2
// GFX11: v_mul_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x6a]
v_mul_f16 v5.l, m0, v2.l
// GFX11: v_mul_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x6a]

v_mul_f16 v5, exec_lo, v2
// GFX11: v_mul_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x6a]
v_mul_f16 v5.l, exec_lo, v2.l
// GFX11: v_mul_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x6a]

v_mul_f16 v5, exec_hi, v2
// GFX11: v_mul_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x6a]
v_mul_f16 v5.l, exec_hi, v2.l
// GFX11: v_mul_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x6a]

v_mul_f16 v5, null, v2
// GFX11: v_mul_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x6a]
v_mul_f16 v5.l, null, v2.l
// GFX11: v_mul_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x6a]

v_mul_f16 v5, -1, v2
// GFX11: v_mul_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x6a]
v_mul_f16 v5.l, -1, v2.l
// GFX11: v_mul_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x6a]

v_mul_f16 v5, 0.5, v2
// GFX11: v_mul_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x6a]
v_mul_f16 v5.l, 0.5, v2.l
// GFX11: v_mul_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x6a]

v_mul_f16 v5, src_scc, v2
// GFX11: v_mul_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x6a]
v_mul_f16 v5.l, src_scc, v2.l
// GFX11: v_mul_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x6a]

v_mul_f16 v127, 0xfe0b, v127
// GFX11: v_mul_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00]
v_mul_f16 v127.l, 0xfe0b, v127.l
// GFX11: v_mul_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00]

v_mul_f16 v5.l, v1.h, v2.l
// GFX11: v_mul_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x6a]

v_mul_f16 v5.l, v127.h, v2.l
// GFX11: v_mul_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x6a]

v_mul_f16 v127.l, 0.5, v127.l
// GFX11: v_mul_f16_e32 v127.l, 0.5, v127.l ; encoding: [0xf0,0xfe,0xfe,0x6a]

v_mul_f16 v5.h, src_scc, v2.h
// GFX11: v_mul_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x6b]

v_mul_f16 v127.h, 0xfe0b, v127.h
// GFX11: v_mul_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00]

v_mul_f32 v5, v1, v2
// GFX11: v_mul_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x10]
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65 changes: 37 additions & 28 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
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Original file line number Diff line number Diff line change
Expand Up @@ -1227,47 +1227,56 @@ v_mul_dx9_zero_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:
v_mul_dx9_zero_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_mul_dx9_zero_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30]

v_mul_f16 v5, v1, v2 quad_perm:[3,2,1,0]
// GFX11: v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff]
v_mul_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff]

v_mul_f16 v5, v1, v2 quad_perm:[0,1,2,3]
// GFX11: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff]
v_mul_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff]

v_mul_f16 v5, v1, v2 row_mirror
// GFX11: v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff]
v_mul_f16 v5.l, v1.l, v2.l row_mirror
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff]

v_mul_f16 v5, v1, v2 row_half_mirror
// GFX11: v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff]
v_mul_f16 v5.l, v1.l, v2.l row_half_mirror
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff]

v_mul_f16 v5, v1, v2 row_shl:1
// GFX11: v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff]
v_mul_f16 v5.l, v1.l, v2.l row_shl:1
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff]

v_mul_f16 v5, v1, v2 row_shl:15
// GFX11: v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff]
v_mul_f16 v5.l, v1.l, v2.l row_shl:15
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff]

v_mul_f16 v5, v1, v2 row_shr:1
// GFX11: v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff]
v_mul_f16 v5.l, v1.l, v2.l row_shr:1
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff]

v_mul_f16 v5, v1, v2 row_shr:15
// GFX11: v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff]
v_mul_f16 v5.l, v1.l, v2.l row_shr:15
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff]

v_mul_f16 v5, v1, v2 row_ror:1
// GFX11: v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff]
v_mul_f16 v5.l, v1.l, v2.l row_ror:1
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff]

v_mul_f16 v5, v1, v2 row_ror:15
// GFX11: v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff]
v_mul_f16 v5.l, v1.l, v2.l row_ror:15
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff]

v_mul_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
// GFX11: v_mul_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff]
v_mul_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff]

v_mul_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
// GFX11: v_mul_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01]
v_mul_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01]

v_mul_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
// GFX11: v_mul_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13]
v_mul_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13]

v_mul_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_mul_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30]
v_mul_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
// GFX11: v_mul_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30]

v_mul_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
// GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x5f,0x01,0x01]

v_mul_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
// GFX11: v_mul_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x6b,0x81,0x60,0x09,0x13]

v_mul_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_mul_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x6b,0xff,0x6f,0xf5,0x30]

v_mul_f32 v5, v1, v2 quad_perm:[3,2,1,0]
// GFX11: v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff]
Expand Down
21 changes: 15 additions & 6 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
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Original file line number Diff line number Diff line change
Expand Up @@ -271,14 +271,23 @@ v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
v_mul_dx9_zero_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_mul_dx9_zero_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00]

v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
v_mul_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]

v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
// GFX11: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
v_mul_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]

v_mul_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_mul_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00]
v_mul_f16 v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
// GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00]

v_mul_f16 v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x77,0x39,0x05]

v_mul_f16 v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
// GFX11: v_mul_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0b,0x6b,0x81,0x77,0x39,0x05]

v_mul_f16 v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_mul_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x6b,0xff,0x00,0x00,0x00]

v_mul_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_mul_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05]
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63 changes: 45 additions & 18 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
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Original file line number Diff line number Diff line change
Expand Up @@ -227,32 +227,59 @@ v_min_f16_e32 v5, v1, v255
v_min_f16_e32 v5, v255, v2
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode

v_mul_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
v_mul_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction

v_mul_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
v_mul_f16_dpp v255.h, v1.h, v2.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction

v_mul_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
v_mul_f16_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction

v_mul_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
v_mul_f16_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction

v_mul_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
v_mul_f16_dpp v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction

v_mul_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
v_mul_f16_dpp v5.h, v1.h, v255.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction

v_mul_f16_e32 v255, v1, v2
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
v_mul_f16_dpp v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction

v_mul_f16_e32 v5, v1, v255
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
v_mul_f16_dpp v5.h, v255.h, v2.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction

v_mul_f16_e32 v5, v255, v2
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
v_mul_f16_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction

v_mul_f16_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction

v_mul_f16_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction

v_mul_f16_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction

v_mul_f16_e32 v255.h, v1.h, v2.h
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction

v_mul_f16_e32 v255.l, v1.l, v2.l
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction

v_mul_f16_e32 v5.h, v1.h, v255.h
// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction

v_mul_f16_e32 v5.h, v255.h, v2.h
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction

v_mul_f16_e32 v5.l, v1.l, v255.l
// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction

v_mul_f16_e32 v5.l, v255.l, v2.l
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction

v_sub_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
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