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[AMDGPU][True16][MC] test update for v_mul_f16 in true16 #119314

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Merged
broxigarchen merged 1 commit into from
Dec 17, 2024
Merged

[AMDGPU][True16][MC] test update for v_mul_f16 in true16 #119314

broxigarchen merged 1 commit into from
Dec 17, 2024

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@broxigarchen broxigarchen commented Dec 10, 2024

This is a NFC change. Update mc test for v_mul_f16 in true16 format.

MC source change was done by previous patch and automatically enabled by t16 pesudo

@broxigarchen broxigarchen marked this pull request as ready for review December 10, 2024 02:49
@llvmbot llvmbot added backend:AMDGPU llvm:mc Machine (object) code labels Dec 10, 2024
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llvmbot commented Dec 10, 2024 •
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@llvm/pr-subscribers-backend-amdgpu

@llvm/pr-subscribers-mc

Author: Brox Chen (broxigarchen)

Changes

This is a NFC change. Update mc test for v_mul_f16 in true16 format.

MC source change was done by previous patch and automatically enabled by t16 pesudo

Patch is 80.90 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119314.diff

17 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/VOP2Instructions.td (+1-2)
  • (modified) llvm/test/MC/AMDGPU/gfx11_asm_vop2.s (+45-30)
  • (modified) llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s (+37-28)
  • (modified) llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s (+15-6)
  • (modified) llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s (+45-18)
  • (modified) llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s (+45-18)
  • (modified) llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s (+40-28)
  • (modified) llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s (+20-8)
  • (modified) llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s (+39-30)
  • (modified) llvm/test/MC/AMDGPU/gfx12_asm_vop2.s (+42-30)
  • (modified) llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s (+34-28)
  • (modified) llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s (+12-6)
  • (modified) llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s (+45-18)
  • (modified) llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s (+45-18)
  • (modified) llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s (+39-30)
  • (modified) llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s (+44-32)
  • (modified) llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s (+24-12)
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 384fec0079a5d9..355528a1f92951 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -1822,8 +1822,7 @@ defm V_ADD_F16             : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x032, "v
 defm V_SUB_F16             : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x033, "v_sub_f16">;
 defm V_SUBREV_F16_t16      : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
 defm V_SUBREV_F16_fake16   : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
-defm V_MUL_F16_t16         : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">;
-defm V_MUL_F16_fake16      : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">;
+defm V_MUL_F16             : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x035, "v_mul_f16">;
 defm V_FMAC_F16            : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x036, "v_fmac_f16">;
 defm V_LDEXP_F16_t16       : VOP2_Real_FULL_t16_gfx11_gfx12<0x03b, "v_ldexp_f16">;
 defm V_LDEXP_F16_fake16    : VOP2_Real_FULL_t16_gfx11_gfx12<0x03b, "v_ldexp_f16">;
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
index cb7b71935e22ae..440c7201f541b0 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
@@ -1582,50 +1582,65 @@ v_mul_dx9_zero_f32 v5, src_scc, v2
 v_mul_dx9_zero_f32 v255, 0xaf123456, v255
 // GFX11: v_mul_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf]
 
-v_mul_f16 v5, v1, v2
-// GFX11: v_mul_f16_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x6a]
+v_mul_f16 v5.l, v1.l, v2.l
+// GFX11: v_mul_f16_e32 v5.l, v1.l, v2.l          ; encoding: [0x01,0x05,0x0a,0x6a]
 
-v_mul_f16 v5, v127, v2
-// GFX11: v_mul_f16_e32 v5, v127, v2              ; encoding: [0x7f,0x05,0x0a,0x6a]
+v_mul_f16 v5.l, v127.l, v2.l
+// GFX11: v_mul_f16_e32 v5.l, v127.l, v2.l        ; encoding: [0x7f,0x05,0x0a,0x6a]
 
-v_mul_f16 v5, s1, v2
-// GFX11: v_mul_f16_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x6a]
+v_mul_f16 v5.l, s1, v2.l
+// GFX11: v_mul_f16_e32 v5.l, s1, v2.l            ; encoding: [0x01,0x04,0x0a,0x6a]
 
-v_mul_f16 v5, s105, v2
-// GFX11: v_mul_f16_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x6a]
+v_mul_f16 v5.l, s105, v2.l
+// GFX11: v_mul_f16_e32 v5.l, s105, v2.l          ; encoding: [0x69,0x04,0x0a,0x6a]
 
-v_mul_f16 v5, vcc_lo, v2
-// GFX11: v_mul_f16_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x6a]
+v_mul_f16 v5.l, vcc_lo, v2.l
+// GFX11: v_mul_f16_e32 v5.l, vcc_lo, v2.l        ; encoding: [0x6a,0x04,0x0a,0x6a]
 
-v_mul_f16 v5, vcc_hi, v2
-// GFX11: v_mul_f16_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x6a]
+v_mul_f16 v5.l, vcc_hi, v2.l
+// GFX11: v_mul_f16_e32 v5.l, vcc_hi, v2.l        ; encoding: [0x6b,0x04,0x0a,0x6a]
 
-v_mul_f16 v5, ttmp15, v2
-// GFX11: v_mul_f16_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x6a]
+v_mul_f16 v5.l, ttmp15, v2.l
+// GFX11: v_mul_f16_e32 v5.l, ttmp15, v2.l        ; encoding: [0x7b,0x04,0x0a,0x6a]
 
-v_mul_f16 v5, m0, v2
-// GFX11: v_mul_f16_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x6a]
+v_mul_f16 v5.l, m0, v2.l
+// GFX11: v_mul_f16_e32 v5.l, m0, v2.l            ; encoding: [0x7d,0x04,0x0a,0x6a]
 
-v_mul_f16 v5, exec_lo, v2
-// GFX11: v_mul_f16_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x6a]
+v_mul_f16 v5.l, exec_lo, v2.l
+// GFX11: v_mul_f16_e32 v5.l, exec_lo, v2.l       ; encoding: [0x7e,0x04,0x0a,0x6a]
 
-v_mul_f16 v5, exec_hi, v2
-// GFX11: v_mul_f16_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x6a]
+v_mul_f16 v5.l, exec_hi, v2.l
+// GFX11: v_mul_f16_e32 v5.l, exec_hi, v2.l       ; encoding: [0x7f,0x04,0x0a,0x6a]
 
-v_mul_f16 v5, null, v2
-// GFX11: v_mul_f16_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x6a]
+v_mul_f16 v5.l, null, v2.l
+// GFX11: v_mul_f16_e32 v5.l, null, v2.l          ; encoding: [0x7c,0x04,0x0a,0x6a]
 
-v_mul_f16 v5, -1, v2
-// GFX11: v_mul_f16_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x6a]
+v_mul_f16 v5.l, -1, v2.l
+// GFX11: v_mul_f16_e32 v5.l, -1, v2.l            ; encoding: [0xc1,0x04,0x0a,0x6a]
 
-v_mul_f16 v5, 0.5, v2
-// GFX11: v_mul_f16_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x6a]
+v_mul_f16 v5.l, 0.5, v2.l
+// GFX11: v_mul_f16_e32 v5.l, 0.5, v2.l           ; encoding: [0xf0,0x04,0x0a,0x6a]
 
-v_mul_f16 v5, src_scc, v2
-// GFX11: v_mul_f16_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x6a]
+v_mul_f16 v5.l, src_scc, v2.l
+// GFX11: v_mul_f16_e32 v5.l, src_scc, v2.l       ; encoding: [0xfd,0x04,0x0a,0x6a]
 
-v_mul_f16 v127, 0xfe0b, v127
-// GFX11: v_mul_f16_e32 v127, 0xfe0b, v127        ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00]
+v_mul_f16 v127.l, 0xfe0b, v127.l
+// GFX11: v_mul_f16_e32 v127.l, 0xfe0b, v127.l    ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00]
+
+v_mul_f16 v5.l, v1.h, v2.l
+// GFX11: v_mul_f16_e32 v5.l, v1.h, v2.l          ; encoding: [0x81,0x05,0x0a,0x6a]
+
+v_mul_f16 v5.l, v127.h, v2.l
+// GFX11: v_mul_f16_e32 v5.l, v127.h, v2.l        ; encoding: [0xff,0x05,0x0a,0x6a]
+
+v_mul_f16 v127.l, 0.5, v127.l
+// GFX11: v_mul_f16_e32 v127.l, 0.5, v127.l       ; encoding: [0xf0,0xfe,0xfe,0x6a]
+
+v_mul_f16 v5.h, src_scc, v2.h
+// GFX11: v_mul_f16_e32 v5.h, src_scc, v2.h       ; encoding: [0xfd,0x04,0x0b,0x6b]
+
+v_mul_f16 v127.h, 0xfe0b, v127.h
+// GFX11: v_mul_f16_e32 v127.h, 0xfe0b, v127.h    ; encoding: [0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00]
 
 v_mul_f32 v5, v1, v2
 // GFX11: v_mul_f32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x10]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
index 00353c4cdcb496..f2d34ab6457af2 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
@@ -1227,47 +1227,56 @@ v_mul_dx9_zero_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:
 v_mul_dx9_zero_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 // GFX11: v_mul_dx9_zero_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30]
 
-v_mul_f16 v5, v1, v2 quad_perm:[3,2,1,0]
-// GFX11: v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff]
+v_mul_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff]
 
-v_mul_f16 v5, v1, v2 quad_perm:[0,1,2,3]
-// GFX11: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff]
+v_mul_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff]
 
-v_mul_f16 v5, v1, v2 row_mirror
-// GFX11: v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff]
+v_mul_f16 v5.l, v1.l, v2.l row_mirror
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff]
 
-v_mul_f16 v5, v1, v2 row_half_mirror
-// GFX11: v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff]
+v_mul_f16 v5.l, v1.l, v2.l row_half_mirror
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff]
 
-v_mul_f16 v5, v1, v2 row_shl:1
-// GFX11: v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff]
+v_mul_f16 v5.l, v1.l, v2.l row_shl:1
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff]
 
-v_mul_f16 v5, v1, v2 row_shl:15
-// GFX11: v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff]
+v_mul_f16 v5.l, v1.l, v2.l row_shl:15
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff]
 
-v_mul_f16 v5, v1, v2 row_shr:1
-// GFX11: v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff]
+v_mul_f16 v5.l, v1.l, v2.l row_shr:1
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff]
 
-v_mul_f16 v5, v1, v2 row_shr:15
-// GFX11: v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff]
+v_mul_f16 v5.l, v1.l, v2.l row_shr:15
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff]
 
-v_mul_f16 v5, v1, v2 row_ror:1
-// GFX11: v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff]
+v_mul_f16 v5.l, v1.l, v2.l row_ror:1
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff]
 
-v_mul_f16 v5, v1, v2 row_ror:15
-// GFX11: v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff]
+v_mul_f16 v5.l, v1.l, v2.l row_ror:15
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff]
 
-v_mul_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// GFX11: v_mul_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff]
+v_mul_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff]
 
-v_mul_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX11: v_mul_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01]
+v_mul_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01]
 
-v_mul_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX11: v_mul_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13]
+v_mul_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13]
 
-v_mul_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX11: v_mul_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30]
+v_mul_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
+// GFX11: v_mul_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30]
+
+v_mul_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x5f,0x01,0x01]
+
+v_mul_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: v_mul_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x6b,0x81,0x60,0x09,0x13]
+
+v_mul_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: v_mul_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x6b,0xff,0x6f,0xf5,0x30]
 
 v_mul_f32 v5, v1, v2 quad_perm:[3,2,1,0]
 // GFX11: v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
index 489e6d8c9d63a9..22974f7a4e517b 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
@@ -271,14 +271,23 @@ v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
 v_mul_dx9_zero_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
 // GFX11: v_mul_dx9_zero_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00]
 
-v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
+v_mul_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
 
-v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX11: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
+v_mul_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
 
-v_mul_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX11: v_mul_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00]
+v_mul_f16 v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
+// GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00]
+
+v_mul_f16 v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x77,0x39,0x05]
+
+v_mul_f16 v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: v_mul_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0b,0x6b,0x81,0x77,0x39,0x05]
+
+v_mul_f16 v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: v_mul_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x6b,0xff,0x00,0x00,0x00]
 
 v_mul_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: v_mul_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
index e5504074079e50..6b2e72e4c1146f 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
@@ -227,32 +227,59 @@ v_min_f16_e32 v5, v1, v255
 v_min_f16_e32 v5, v255, v2
 // GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
 
-v_mul_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_mul_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
 
-v_mul_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_mul_f16_dpp v255.h, v1.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
 
-v_mul_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_mul_f16_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
 
-v_mul_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_mul_f16_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
 
-v_mul_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_mul_f16_dpp v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction
 
-v_mul_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_mul_f16_dpp v5.h, v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction
 
-v_mul_f16_e32 v255, v1, v2
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_mul_f16_dpp v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
 
-v_mul_f16_e32 v5, v1, v255
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_mul_f16_dpp v5.h, v255.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
 
-v_mul_f16_e32 v5, v255, v2
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_mul_f16_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction
+
+v_mul_f16_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction
+
+v_mul_f16_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
+
+v_mul_f16_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
+
+v_mul_f16_e32 v255.h, v1.h, v2.h
+// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
+
+v_mul_f16_e32 v255.l, v1.l, v2.l
+// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
+
+v_mul_f16_e32 v5.h, v1.h, v255.h
+// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction
+
+v_mul_f16_e32 v5.h, v255.h, v2.h
+// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
+
+v_mul_f16_e32 v5.l, v1.l, v255.l
+// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction
+
+v_mul_f16_e32 v5.l, v255.l, v2.l
+// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
 
 v_sub_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
index 63394502ec14ed..5a87ee451272fc 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
@@ -146,32 +146,59 @@ v_min_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
 v_min_f16 v5, v255, v2 quad_perm:[3,2,1,0]
 // GFX11: v_min_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
 
-v_mul_f16 v255, v1, v2
-// GFX11: v_mul_f16_e64 v255, v1, v2              ; encoding: [0xff,0x00,0x35,0xd5,0x01,0x05,0x02,0x00]
+v_mul_f16 v255.h, v1.h, v2.h
+// GFX11: v_mul_f16_e64 v255.h, v1.h, v2.h op_sel:[1,1,1] ; encoding: [0xff,0x58,0x35,0xd5,0x01,0x05,0x02,0x00]
 
-v_mul_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_mul_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_mul_f16 v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_mul_f16_e64_dpp v255.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x58,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
 
-v_mul_f16 v255, v1, v2 quad_perm:[3,2,1,0]
-// GFX11: v_mul_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+v_mul_f16 v255.h, v1.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: v_mul_f16_e64_dpp v255.h, v1.h, v2.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x58,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
 
-v_mul_f16 v5, v1, v255
-// GFX11: v_mul_f16_e64 v5, v1, v255              ; encoding: [0x05,0x00,0x35,0xd5,0x01,0xff,0x03,0x00]
+v_mul_f16 v255.l, v1.l, v2.l
+// GFX11: v_mul_f16_e64 v255.l, v1.l, v2.l        ; encoding: [0xff,0x00,0x35,0xd5,0x01,0x05,0x02,0x00]
 
-v_mul_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_mul_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
+v_mul_f16 v2...
[truncated]

Sisyph
Sisyph approved these changes Dec 10, 2024
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It looks like the test order is different in the t16_err and t16_promote that what is already here, which makes it harder to read the diff in those files. I checked this one, but for future patches maybe you can make the order match. In other files the order matches. LGTM

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broxigarchen commented Dec 10, 2024 •
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It looks like the test order is different in the t16_err and t16_promote that what is already here, which makes it harder to read the diff in those files. I checked this one, but for future patches maybe you can make the order match. In other files the order matches. LGTM

Hi Joe. These two files are sorted in alphebetic order both upstream and downstream ( we previously run update script with a "--sort" to resolve the merge problem). Do you think it's necessary to refactor this part?

@broxigarchen broxigarchen merged commit f9a9173 into llvm:main Dec 17, 2024
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@broxigarchen broxigarchen requested a review from kosarev January 10, 2025 15:23
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