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AMDGPU: Reduce AddedComplexity on canonicalize pattern #119796

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Merged
merged 2 commits into from
Jan 7, 2025
Merged

AMDGPU: Reduce AddedComplexity on canonicalize pattern #119796

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AMDGPU: Remove large, negative AddedComplexity from minimum/maximum p…
arsenm Dec 12, 2024
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AMDGPU: Reduce AddedComplexity on canonicalize pattern
arsenm Dec 12, 2024
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -3055,7 +3055,7 @@ def : GCNPat<
(V_BFREV_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$a, sub0))), sub1)>;

// If fcanonicalize's operand is implicitly canonicalized, we only need a copy.
let AddedComplexity = 1000 in {
let AddedComplexity = 8 in {
foreach vt = [f16, v2f16, f32, v2f32, f64] in {
def : GCNPat<
(fcanonicalize (vt is_canonicalized:$src)),
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SOPInstructions.td
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Expand Up @@ -948,7 +948,7 @@ let SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1,

// On GFX12 MIN/MAX instructions do not read MODE register.
let SubtargetPredicate = isGFX12Plus, mayRaiseFPException = 1, isCommutable = 1,
isReMaterializable = 1, SchedRW = [WriteSFPU] in {
isReMaterializable = 1, SchedRW = [WriteSFPU], AddedComplexity = 17 in {
def S_MINIMUM_F32 : SOP2_F32_Inst<"s_minimum_f32", fminimum>;
def S_MAXIMUM_F32 : SOP2_F32_Inst<"s_maximum_f32", fmaximum>;
def S_MINIMUM_F16 : SOP2_F16_Inst<"s_minimum_f16", fminimum>;
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6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/VOP3Instructions.td
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Expand Up @@ -167,7 +167,7 @@ defm V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", V_MUL_PROF<VOP_I32_I32_I32>>;
defm V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", V_MUL_PROF<VOP_I32_I32_I32>, mulhs>;
} // End SchedRW = [WriteIntMul]

let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in {
let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0, AddedComplexity = 1 in {
defm V_MINIMUM_F32 : VOP3Inst <"v_minimum_f32", VOP3_Profile<VOP_F32_F32_F32>, DivergentBinFrag<fminimum>>;
defm V_MAXIMUM_F32 : VOP3Inst <"v_maximum_f32", VOP3_Profile<VOP_F32_F32_F32>, DivergentBinFrag<fmaximum>>;
defm V_MINIMUM_F16 : VOP3Inst <"v_minimum_f16", VOP3_Profile<VOP_F16_F16_F16>, DivergentBinFrag<fminimum>>;
Expand All @@ -177,7 +177,7 @@ let SchedRW = [WriteDoubleAdd] in {
defm V_MINIMUM_F64 : VOP3Inst <"v_minimum_f64", VOP3_Profile<VOP_F64_F64_F64>, fminimum>;
defm V_MAXIMUM_F64 : VOP3Inst <"v_maximum_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaximum>;
} // End SchedRW = [WriteDoubleAdd]
} // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0
} // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0, AddedComplexity = 1

} // End isReMaterializable = 1

Expand Down Expand Up @@ -1561,7 +1561,7 @@ class MinimumMaximumByMinimum3Maximum3<SDPatternOperator node, ValueType vt,
>;

// Prefer the real 2 operand form if legal
let SubtargetPredicate = HasMinimum3Maximum3F32, AddedComplexity = -1000 in {
let SubtargetPredicate = HasMinimum3Maximum3F32 in {
def : MinimumMaximumByMinimum3Maximum3<fminimum, f32, V_MINIMUM3_F32_e64>;
def : MinimumMaximumByMinimum3Maximum3<fmaximum, f32, V_MAXIMUM3_F32_e64>;
}
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