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[Coalescer] Consider NewMI's subreg index when updating lanemask. #121780

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Jan 7, 2025
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[Coalescer] Consider NewMI's subreg index when updating lanemask. #121780

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sdesmalen-arm Jan 6, 2025
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[Coalescer] Consider NewMI's subreg index when updating lanemask.
sdesmalen-arm Dec 17, 2024
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sdesmalen-arm Jan 7, 2025
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15 changes: 8 additions & 7 deletions llvm/lib/CodeGen/RegisterCoalescer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1526,17 +1526,18 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,

// In a situation like the following:
//
// undef %2.subreg:reg = INST %1:reg ; DefMI (rematerializable),
// ; DefSubIdx = subreg
// %3:reg = COPY %2 ; SrcIdx = DstIdx = 0
// .... = SOMEINSTR %3:reg
// undef %2.subreg:reg = INST %1:reg ; DefMI (rematerializable),
// ; Defines only some of lanes,
// ; so DefSubIdx = NewIdx = subreg
// %3:reg = COPY %2 ; Copy full reg
// .... = SOMEINSTR %3:reg ; Use full reg
//
// there are no subranges for %3 so after rematerialization we need
// to explicitly create them. Undefined subranges are removed later on.
if (DefSubIdx && !CP.getSrcIdx() && !CP.getDstIdx() &&
MRI->shouldTrackSubRegLiveness(DstReg) && !DstInt.hasSubRanges()) {
if (NewIdx && !DstInt.hasSubRanges() &&
MRI->shouldTrackSubRegLiveness(DstReg)) {
LaneBitmask FullMask = MRI->getMaxLaneMaskForVReg(DstReg);
LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(DefSubIdx);
LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(NewIdx);
LaneBitmask UnusedLanes = FullMask & ~UsedLanes;
VNInfo::Allocator &Alloc = LIS->getVNInfoAllocator();
DstInt.createSubRangeFrom(Alloc, UsedLanes, DstInt);
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93 changes: 92 additions & 1 deletion llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
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@@ -1,5 +1,5 @@
# RUN: llc -mtriple=aarch64 -o /dev/null -run-pass=register-coalescer -aarch64-enable-subreg-liveness-tracking -debug-only=regalloc %s 2>&1 | FileCheck %s --check-prefix=CHECK-DBG
# RUN: llc -mtriple=aarch64 -verify-machineinstrs -o - -run-pass=register-coalescer -aarch64-enable-subreg-liveness-tracking %s | FileCheck %s --check-prefix=CHECK
# RUN: llc -mtriple=aarch64 -verify-machineinstrs -o /dev/null -run-pass=register-coalescer -aarch64-enable-subreg-liveness-tracking -debug-only=regalloc %s 2>&1 | FileCheck %s --check-prefix=CHECK-DBG
# REQUIRES: asserts

# CHECK-DBG: ********** REGISTER COALESCER **********
Expand Down Expand Up @@ -36,3 +36,94 @@ body: |
RET_ReallyLR

...
# CHECK-DBG: ********** REGISTER COALESCER **********
# CHECK-DBG: ********** Function: reproducer
# CHECK-DBG: ********** JOINING INTERVALS ***********
# CHECK-DBG: ********** INTERVALS **********
# CHECK-DBG: %1 [32r,48B:2)[48B,320r:0)[320r,368B:1) 0@48B-phi 1@320r 2@32r
# CHECK-DBG-SAME: weight:0.000000e+00
# CHECK-DBG: %3 [80r,160B:2)[240r,272B:1)[288r,304B:0)[304B,320r:3) 0@288r 1@240r 2@80r 3@304B-phi
# CHECK-DBG-SAME: L0000000000000080 [288r,304B:0)[304B,320r:3) 0@288r 1@x 2@x 3@304B-phi
# CHECK-DBG-SAME: L0000000000000040 [80r,160B:2)[240r,272B:1)[288r,304B:0)[304B,320r:3) 0@288r 1@240r 2@80r 3@304B-phi
# CHECK-DBG-SAME: weight:0.000000e+00
---
name: reproducer
tracksRegLiveness: true
body: |
bb.0:
%0:gpr32 = MOVi32imm 1
%1:gpr64 = IMPLICIT_DEF

bb.1:

bb.2:
%3:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32

bb.3:
$nzcv = IMPLICIT_DEF
%4:gpr64 = COPY killed %3
Bcc 1, %bb.7, implicit killed $nzcv

bb.4:
$nzcv = IMPLICIT_DEF
Bcc 1, %bb.6, implicit killed $nzcv

bb.5:
%5:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32
%4:gpr64 = COPY killed %5
B %bb.7

bb.6:
%4:gpr64 = COPY $xzr

bb.7:
%7:gpr64 = ADDXrs killed %1, killed %4, 1
%1:gpr64 = COPY killed %7
B %bb.1

...
# CHECK-DBG: ********** REGISTER COALESCER **********
# CHECK-DBG: ********** Function: reproducer2
# CHECK-DBG: ********** JOINING INTERVALS ***********
# CHECK-DBG: ********** INTERVALS **********
# CHECK-DBG: %1 [32r,48B:2)[48B,304r:0)[304r,352B:1) 0@48B-phi 1@304r 2@32r
# CHECK-DBG-SAME: weight:0.000000e+00
# CHECK-DBG: %3 [80r,160B:2)[224r,256B:1)[272r,288B:0)[288B,304r:3) 0@272r 1@224r 2@80r 3@288B-phi
# CHECK-DBG-SAME: L0000000000000080 [224r,256B:1)[272r,288B:0)[288B,304r:3) 0@272r 1@224r 2@x 3@288B-phi
# CHECK-DBG-SAME: L0000000000000040 [80r,160B:2)[224r,256B:1)[272r,288B:0)[288B,304r:3) 0@272r 1@224r 2@80r 3@288B-phi
# CHECK-DBG-SAME: weight:0.000000e+00
---
name: reproducer2
tracksRegLiveness: true
body: |
bb.0:
%0:gpr32 = MOVi32imm 1
%1:gpr64 = IMPLICIT_DEF

bb.1:

bb.2:
%3:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32

bb.3:
$nzcv = IMPLICIT_DEF
%4:gpr64 = COPY killed %3
Bcc 1, %bb.7, implicit killed $nzcv

bb.4:
$nzcv = IMPLICIT_DEF
Bcc 1, %bb.6, implicit killed $nzcv

bb.5:
%4:gpr64 = IMPLICIT_DEF
B %bb.7

bb.6:
%4:gpr64 = COPY $xzr

bb.7:
%5:gpr64 = ADDXrs killed %1, killed %4, 1
%1:gpr64 = COPY killed %5
B %bb.1

...
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