[AArch64] Ensure APAS instruction passes register parameter #121928
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
In PR llvm#112341, the `APAS` instruction was added as part of the Armv9.6-A specification, but it didn't take the Xt register parameter. This change fixes this.
Member
|
@llvm/pr-subscribers-mc Author: Jonathan Thackray (jthackray) ChangesIn PR #112341, the Full diff: https://github.com/llvm/llvm-project/pull/121928.diff 3 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 47c4c6c39565f4..b6fabdb7db59d2 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1804,7 +1804,9 @@ class TMSystemException<bits<3> op1, string asm, list<dag> pattern>
}
class APASI : SimpleSystemI<0, (ins GPR64:$Xt), "apas", "\t$Xt">, Sched<[]> {
+ bits<5> Xt;
let Inst{20-5} = 0b0111001110000000;
+ let Inst{4-0} = Xt;
let DecoderNamespace = "APAS";
}
diff --git a/llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s b/llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s
index baf05f10b9a1e3..093101b6cd8127 100644
--- a/llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s
+++ b/llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s
@@ -2,10 +2,18 @@
// RUN: llvm-mc -triple aarch64 -show-encoding %s | FileCheck %s
.func:
apas x0
+ apas x1
+ apas x2
+ apas x17
+ apas x30
mrs x3, GPCBW_EL3
msr GPCBW_EL3, x4
# CHECK: .func:
-# CHECK-NEXT: apas x0 // encoding: [0x1f,0x70,0x0e,0xd5]
+# CHECK-NEXT: apas x0 // encoding: [0x00,0x70,0x0e,0xd5]
+# CHECK-NEXT: apas x1 // encoding: [0x01,0x70,0x0e,0xd5]
+# CHECK-NEXT: apas x2 // encoding: [0x02,0x70,0x0e,0xd5]
+# CHECK-NEXT: apas x17 // encoding: [0x11,0x70,0x0e,0xd5]
+# CHECK-NEXT: apas x30 // encoding: [0x1e,0x70,0x0e,0xd5]
# CHECK-NEXT: mrs x3, GPCBW_EL3 // encoding: [0xa3,0x21,0x3e,0xd5]
# CHECK-NEXT: msr GPCBW_EL3, x4 // encoding: [0xa4,0x21,0x1e,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
index c5d074bf0394f1..d198771c341b9e 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
@@ -1,10 +1,18 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mc -triple aarch64 -disassemble %s | FileCheck %s
-[0x1f,0x70,0x0e,0xd5]
+[0x00,0x70,0x0e,0xd5]
+[0x01,0x70,0x0e,0xd5]
+[0x02,0x70,0x0e,0xd5]
+[0x11,0x70,0x0e,0xd5]
+[0x1e,0x70,0x0e,0xd5]
[0xa3,0x21,0x3e,0xd5]
[0xa4,0x21,0x1e,0xd5]
-# CHECK: sys #6, c7, c0, #0
+# CHECK: sys #6, c7, c0, #0, x0
+# CHECK-NEXT: sys #6, c7, c0, #0, x1
+# CHECK-NEXT: sys #6, c7, c0, #0, x2
+# CHECK-NEXT: sys #6, c7, c0, #0, x17
+# CHECK-NEXT: sys #6, c7, c0, #0, x30
# CHECK-NEXT: mrs x3, GPCBW_EL3
# CHECK-NEXT: msr GPCBW_EL3, x4
|
Member
|
@llvm/pr-subscribers-backend-aarch64 Author: Jonathan Thackray (jthackray) ChangesIn PR #112341, the Full diff: https://github.com/llvm/llvm-project/pull/121928.diff 3 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 47c4c6c39565f4..b6fabdb7db59d2 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1804,7 +1804,9 @@ class TMSystemException<bits<3> op1, string asm, list<dag> pattern>
}
class APASI : SimpleSystemI<0, (ins GPR64:$Xt), "apas", "\t$Xt">, Sched<[]> {
+ bits<5> Xt;
let Inst{20-5} = 0b0111001110000000;
+ let Inst{4-0} = Xt;
let DecoderNamespace = "APAS";
}
diff --git a/llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s b/llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s
index baf05f10b9a1e3..093101b6cd8127 100644
--- a/llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s
+++ b/llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s
@@ -2,10 +2,18 @@
// RUN: llvm-mc -triple aarch64 -show-encoding %s | FileCheck %s
.func:
apas x0
+ apas x1
+ apas x2
+ apas x17
+ apas x30
mrs x3, GPCBW_EL3
msr GPCBW_EL3, x4
# CHECK: .func:
-# CHECK-NEXT: apas x0 // encoding: [0x1f,0x70,0x0e,0xd5]
+# CHECK-NEXT: apas x0 // encoding: [0x00,0x70,0x0e,0xd5]
+# CHECK-NEXT: apas x1 // encoding: [0x01,0x70,0x0e,0xd5]
+# CHECK-NEXT: apas x2 // encoding: [0x02,0x70,0x0e,0xd5]
+# CHECK-NEXT: apas x17 // encoding: [0x11,0x70,0x0e,0xd5]
+# CHECK-NEXT: apas x30 // encoding: [0x1e,0x70,0x0e,0xd5]
# CHECK-NEXT: mrs x3, GPCBW_EL3 // encoding: [0xa3,0x21,0x3e,0xd5]
# CHECK-NEXT: msr GPCBW_EL3, x4 // encoding: [0xa4,0x21,0x1e,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
index c5d074bf0394f1..d198771c341b9e 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
@@ -1,10 +1,18 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mc -triple aarch64 -disassemble %s | FileCheck %s
-[0x1f,0x70,0x0e,0xd5]
+[0x00,0x70,0x0e,0xd5]
+[0x01,0x70,0x0e,0xd5]
+[0x02,0x70,0x0e,0xd5]
+[0x11,0x70,0x0e,0xd5]
+[0x1e,0x70,0x0e,0xd5]
[0xa3,0x21,0x3e,0xd5]
[0xa4,0x21,0x1e,0xd5]
-# CHECK: sys #6, c7, c0, #0
+# CHECK: sys #6, c7, c0, #0, x0
+# CHECK-NEXT: sys #6, c7, c0, #0, x1
+# CHECK-NEXT: sys #6, c7, c0, #0, x2
+# CHECK-NEXT: sys #6, c7, c0, #0, x17
+# CHECK-NEXT: sys #6, c7, c0, #0, x30
# CHECK-NEXT: mrs x3, GPCBW_EL3
# CHECK-NEXT: msr GPCBW_EL3, x4
|
jthackray
requested review from
CarolineConcatto,
Stylie777,
nasherm,
rgwott and
tmatheson-arm
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
3 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
In PR #112341, the
APASinstruction was added as part of the Armv9.6-A specification, but it didn't take the Xt register parameter. This change fixes this.