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[AArch64] Ensure APAS instruction passes register parameter #121928

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Merged
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Jan 8, 2025
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[AArch64] Ensure APAS instruction passes register parameter #121928

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2 changes: 2 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1804,7 +1804,9 @@ class TMSystemException<bits<3> op1, string asm, list<dag> pattern>
}

class APASI : SimpleSystemI<0, (ins GPR64:$Xt), "apas", "\t$Xt">, Sched<[]> {
bits<5> Xt;
let Inst{20-5} = 0b0111001110000000;
let Inst{4-0} = Xt;
let DecoderNamespace = "APAS";
}

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10 changes: 9 additions & 1 deletion llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s
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Expand Up @@ -2,10 +2,18 @@
// RUN: llvm-mc -triple aarch64 -show-encoding %s | FileCheck %s
.func:
apas x0
apas x1
apas x2
apas x17
apas x30
mrs x3, GPCBW_EL3
msr GPCBW_EL3, x4

# CHECK: .func:
# CHECK-NEXT: apas x0 // encoding: [0x1f,0x70,0x0e,0xd5]
# CHECK-NEXT: apas x0 // encoding: [0x00,0x70,0x0e,0xd5]
# CHECK-NEXT: apas x1 // encoding: [0x01,0x70,0x0e,0xd5]
# CHECK-NEXT: apas x2 // encoding: [0x02,0x70,0x0e,0xd5]
# CHECK-NEXT: apas x17 // encoding: [0x11,0x70,0x0e,0xd5]
# CHECK-NEXT: apas x30 // encoding: [0x1e,0x70,0x0e,0xd5]
# CHECK-NEXT: mrs x3, GPCBW_EL3 // encoding: [0xa3,0x21,0x3e,0xd5]
# CHECK-NEXT: msr GPCBW_EL3, x4 // encoding: [0xa4,0x21,0x1e,0xd5]
12 changes: 10 additions & 2 deletions llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
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@@ -1,10 +1,18 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mc -triple aarch64 -disassemble %s | FileCheck %s

[0x1f,0x70,0x0e,0xd5]
[0x00,0x70,0x0e,0xd5]
[0x01,0x70,0x0e,0xd5]
[0x02,0x70,0x0e,0xd5]
[0x11,0x70,0x0e,0xd5]
[0x1e,0x70,0x0e,0xd5]
[0xa3,0x21,0x3e,0xd5]
[0xa4,0x21,0x1e,0xd5]

# CHECK: sys #6, c7, c0, #0
# CHECK: sys #6, c7, c0, #0, x0
# CHECK-NEXT: sys #6, c7, c0, #0, x1
# CHECK-NEXT: sys #6, c7, c0, #0, x2
# CHECK-NEXT: sys #6, c7, c0, #0, x17
# CHECK-NEXT: sys #6, c7, c0, #0, x30
# CHECK-NEXT: mrs x3, GPCBW_EL3
# CHECK-NEXT: msr GPCBW_EL3, x4
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