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[AggressiveInstCombine] Merge consecutive loads of mixed sizes #129263

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Merged
merged 12 commits into from
Mar 5, 2025
Merged

[AggressiveInstCombine] Merge consecutive loads of mixed sizes #129263

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343b383
[InstCombine] Add pre-commit tests. NFC.
Cancelll Feb 28, 2025
16243e2
[InstCombine] Handle mixsize consecutive loads
Cancelll Feb 28, 2025
35098bf
[InstCombine] Modify the comment accordingly. NFC.
Cancelll Feb 28, 2025
f386a1d
[AggressiveInstCombine] Add more tests. NFC.
Cancelll Mar 2, 2025
3ca730d
[AggressiveInstCombine] Add check for LoadSize2 and remove the power …
Cancelll Mar 2, 2025
f45e2db
[AggressiveInstCombine] Modify the comment accordingly. NFC.
Cancelll Mar 2, 2025
b03986b
[AggressiveInstCombine] Rename two tests to more clearly show the pur…
Cancelll Mar 2, 2025
7c7c8fc
[AggressiveInstCombine] Add more negative tests. NFC.
Cancelll Mar 2, 2025
f1e2914
[AggressiveInstCombine] Check load sizes equal to store sizes.
Cancelll Mar 2, 2025
ad75d16
[AggressiveInstCombine] Address review comments. NFC.
Cancelll Mar 3, 2025
1541a9b
[AggressiveInstCombine] Remove unnecessarily repeated tests. NFC.
Cancelll Mar 3, 2025
79aa2da
[AggressiveInstCombine] Fix the format issue. NFC.
Cancelll Mar 5, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -675,10 +675,10 @@ static bool foldLoadsRecursive(Value *V, LoadOps &LOps, const DataLayout &DL,
Load2Ptr->stripAndAccumulateConstantOffsets(DL, Offset2,
/* AllowNonInbounds */ true);

// Verify if both loads have same base pointers and load sizes are same.
// Verify if both loads have same base pointers
uint64_t LoadSize1 = LI1->getType()->getPrimitiveSizeInBits();
uint64_t LoadSize2 = LI2->getType()->getPrimitiveSizeInBits();
if (Load1Ptr != Load2Ptr || LoadSize1 != LoadSize2)
if (Load1Ptr != Load2Ptr)
return false;

// Support Loadsizes greater or equal to 8bits and only power of 2.
Expand Down
280 changes: 210 additions & 70 deletions llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1529,20 +1529,24 @@ define i64 @eggs(ptr noundef readonly %arg) {
}

define i32 @loadCombine_4consecutive_mixsize1(ptr %p) {
; ALL-LABEL: @loadCombine_4consecutive_mixsize1(
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; ALL-NEXT: ret i32 [[O2]]
; LE-LABEL: @loadCombine_4consecutive_mixsize1(
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
; LE-NEXT: ret i32 [[L1]]
;
; BE-LABEL: @loadCombine_4consecutive_mixsize1(
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
; BE-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; BE-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: ret i32 [[O2]]
;
%p1 = getelementptr i8, ptr %p, i32 2
%p2 = getelementptr i8, ptr %p, i32 3
Expand All @@ -1563,20 +1567,24 @@ define i32 @loadCombine_4consecutive_mixsize1(ptr %p) {
}

define i32 @loadCombine_4consecutive_mixsize1_BE(ptr %p) {
; ALL-LABEL: @loadCombine_4consecutive_mixsize1_BE(
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; ALL-NEXT: [[S1:%.*]] = shl i32 [[E1]], 16
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; ALL-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]]
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[E3]]
; ALL-NEXT: ret i32 [[O2]]
; LE-LABEL: @loadCombine_4consecutive_mixsize1_BE(
; LE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
; LE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
; LE-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
; LE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; LE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; LE-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
; LE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; LE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; LE-NEXT: [[S1:%.*]] = shl i32 [[E1]], 16
; LE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; LE-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]]
; LE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[E3]]
; LE-NEXT: ret i32 [[O2]]
;
; BE-LABEL: @loadCombine_4consecutive_mixsize1_BE(
; BE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
; BE-NEXT: ret i32 [[L1]]
;
%p1 = getelementptr i8, ptr %p, i32 2
%p2 = getelementptr i8, ptr %p, i32 3
Expand All @@ -1597,20 +1605,24 @@ define i32 @loadCombine_4consecutive_mixsize1_BE(ptr %p) {
}

define i32 @loadCombine_4consecutive_rev_mixsize1(ptr %p) {
; ALL-LABEL: @loadCombine_4consecutive_rev_mixsize1(
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P2]], align 1
; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P3]], align 1
; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
; ALL-NEXT: [[O1:%.*]] = or i32 [[S3]], [[S2]]
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[E1]]
; ALL-NEXT: ret i32 [[O2]]
; LE-LABEL: @loadCombine_4consecutive_rev_mixsize1(
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
; LE-NEXT: ret i32 [[L1]]
;
; BE-LABEL: @loadCombine_4consecutive_rev_mixsize1(
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
; BE-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P2]], align 1
; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P3]], align 1
; BE-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
; BE-NEXT: [[O1:%.*]] = or i32 [[S3]], [[S2]]
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[E1]]
; BE-NEXT: ret i32 [[O2]]
;
%p2 = getelementptr i8, ptr %p, i32 2
%p3 = getelementptr i8, ptr %p, i32 3
Expand All @@ -1631,20 +1643,24 @@ define i32 @loadCombine_4consecutive_rev_mixsize1(ptr %p) {
}

define i32 @loadCombine_4consecutive_rev_mixsize1_BE(ptr %p) {
; ALL-LABEL: @loadCombine_4consecutive_rev_mixsize1_BE(
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P2]], align 1
; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P3]], align 1
; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; ALL-NEXT: [[S1:%.*]] = shl i32 [[E1]], 16
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; ALL-NEXT: [[O1:%.*]] = or i32 [[E3]], [[S2]]
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S1]]
; ALL-NEXT: ret i32 [[O2]]
; LE-LABEL: @loadCombine_4consecutive_rev_mixsize1_BE(
; LE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
; LE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
; LE-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
; LE-NEXT: [[L2:%.*]] = load i8, ptr [[P2]], align 1
; LE-NEXT: [[L3:%.*]] = load i8, ptr [[P3]], align 1
; LE-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
; LE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; LE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; LE-NEXT: [[S1:%.*]] = shl i32 [[E1]], 16
; LE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; LE-NEXT: [[O1:%.*]] = or i32 [[E3]], [[S2]]
; LE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S1]]
; LE-NEXT: ret i32 [[O2]]
;
; BE-LABEL: @loadCombine_4consecutive_rev_mixsize1_BE(
; BE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
; BE-NEXT: ret i32 [[L1]]
;
%p2 = getelementptr i8, ptr %p, i32 2
%p3 = getelementptr i8, ptr %p, i32 3
Expand All @@ -1665,20 +1681,24 @@ define i32 @loadCombine_4consecutive_rev_mixsize1_BE(ptr %p) {
}

define i32 @loadCombine_4consecutive_mixsize2(ptr %p) {
; ALL-LABEL: @loadCombine_4consecutive_mixsize2(
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; ALL-NEXT: [[L3:%.*]] = load i16, ptr [[P2]], align 2
; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; ALL-NEXT: [[E3:%.*]] = zext i16 [[L3]] to i32
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; ALL-NEXT: ret i32 [[O2]]
; LE-LABEL: @loadCombine_4consecutive_mixsize2(
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
; LE-NEXT: ret i32 [[L1]]
;
; BE-LABEL: @loadCombine_4consecutive_mixsize2(
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; BE-NEXT: [[L3:%.*]] = load i16, ptr [[P2]], align 2
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; BE-NEXT: [[E3:%.*]] = zext i16 [[L3]] to i32
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: ret i32 [[O2]]
;
%p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2
Expand All @@ -1698,6 +1718,126 @@ define i32 @loadCombine_4consecutive_mixsize2(ptr %p) {
ret i32 %o2
}

define i32 @loadCombine_4consecutive_mixsize3(ptr %p) {
; LE-LABEL: @loadCombine_4consecutive_mixsize3(
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
; LE-NEXT: ret i32 [[L1]]
;
; BE-LABEL: @loadCombine_4consecutive_mixsize3(
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; BE-NEXT: [[L2:%.*]] = load i16, ptr [[P1]], align 2
; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
; BE-NEXT: [[E2:%.*]] = zext i16 [[L2]] to i32
; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: ret i32 [[O2]]
;
%p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 3
%l1 = load i8, ptr %p
%l2 = load i16, ptr %p1
%l3 = load i8, ptr %p2

%e1 = zext i8 %l1 to i32
%e2 = zext i16 %l2 to i32
%e3 = zext i8 %l3 to i32

%s2 = shl i32 %e2, 8
%s3 = shl i32 %e3, 24

%o1 = or i32 %e1, %s2
%o2 = or i32 %o1, %s3
ret i32 %o2
}

define i16 @loadCombine_mixsize_4bit(ptr %p) {
; ALL-LABEL: @loadCombine_mixsize_4bit(
; ALL-NEXT: [[P1:%.*]] = getelementptr i4, ptr [[P:%.*]], i32 2
; ALL-NEXT: [[P2:%.*]] = getelementptr i4, ptr [[P]], i32 3
; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; ALL-NEXT: [[L2:%.*]] = load i4, ptr [[P1]], align 1
; ALL-NEXT: [[L3:%.*]] = load i4, ptr [[P2]], align 1
; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i16
; ALL-NEXT: [[E2:%.*]] = zext i4 [[L2]] to i16
; ALL-NEXT: [[E3:%.*]] = zext i4 [[L3]] to i16
; ALL-NEXT: [[S2:%.*]] = shl i16 [[E2]], 8
; ALL-NEXT: [[S3:%.*]] = shl i16 [[E3]], 12
; ALL-NEXT: [[O1:%.*]] = or i16 [[E1]], [[S2]]
; ALL-NEXT: [[O2:%.*]] = or i16 [[O1]], [[S3]]
; ALL-NEXT: ret i16 [[O2]]
;
%p1 = getelementptr i4, ptr %p, i32 2
%p2 = getelementptr i4, ptr %p, i32 3
%l1 = load i8, ptr %p
%l2 = load i4, ptr %p1
%l3 = load i4, ptr %p2

%e1 = zext i8 %l1 to i16
%e2 = zext i4 %l2 to i16
%e3 = zext i4 %l3 to i16

%s2 = shl i16 %e2, 8
%s3 = shl i16 %e3, 12

%o1 = or i16 %e1, %s2
%o2 = or i16 %o1, %s3
ret i16 %o2
}

define i64 @loadCombine_8consecutive_mixsize(ptr %p) {
; LE-LABEL: @loadCombine_8consecutive_mixsize(
; LE-NEXT: [[L1:%.*]] = load i64, ptr [[P:%.*]], align 1
; LE-NEXT: ret i64 [[L1]]
;
; BE-LABEL: @loadCombine_8consecutive_mixsize(
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2
; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 4
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; BE-NEXT: [[L3:%.*]] = load i16, ptr [[P2]], align 2
; BE-NEXT: [[L4:%.*]] = load i32, ptr [[P3]], align 4
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i64
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i64
; BE-NEXT: [[E3:%.*]] = zext i16 [[L3]] to i64
; BE-NEXT: [[E4:%.*]] = zext i32 [[L4]] to i64
; BE-NEXT: [[S2:%.*]] = shl i64 [[E2]], 8
; BE-NEXT: [[S3:%.*]] = shl i64 [[E3]], 16
; BE-NEXT: [[S4:%.*]] = shl i64 [[E4]], 32
; BE-NEXT: [[O1:%.*]] = or i64 [[E1]], [[S2]]
; BE-NEXT: [[O2:%.*]] = or i64 [[O1]], [[S3]]
; BE-NEXT: [[O3:%.*]] = or i64 [[O2]], [[S4]]
; BE-NEXT: ret i64 [[O3]]
;
%p1 = getelementptr i8, ptr %p, i64 1
%p2 = getelementptr i8, ptr %p, i64 2
%p3 = getelementptr i8, ptr %p, i64 4
%l1 = load i8, ptr %p
%l2 = load i8, ptr %p1
%l3 = load i16, ptr %p2
%l4 = load i32, ptr %p3

%e1 = zext i8 %l1 to i64
%e2 = zext i8 %l2 to i64
%e3 = zext i16 %l3 to i64
%e4 = zext i32 %l4 to i64

%s2 = shl i64 %e2, 8
%s3 = shl i64 %e3, 16
%s4 = shl i64 %e4, 32

%o1 = or i64 %e1, %s2
%o2 = or i64 %o1, %s3
%o3 = or i64 %o2, %s4
ret i64 %o3
}

define i32 @loadCombine_4consecutive_lower_index_comes_before(ptr %p) {
; LE-LABEL: @loadCombine_4consecutive_lower_index_comes_before(
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
Expand Down
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