[AMDGPU][MC] Don't crash on decoding invalid SOP1 ssrc0 operands. #130302
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These are encoded as 8-bit fields.
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@llvm/pr-subscribers-mc @llvm/pr-subscribers-backend-amdgpu Author: Ivan Kosarev (kosarev) ChangesThese are encoded as 8-bit fields. Full diff: https://github.com/llvm/llvm-project/pull/130302.diff 3 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index afed8b999d8eb..728ce125eba2d 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -176,9 +176,12 @@ static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize,
// Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to
// get register class. Used by SGPR only operands.
-#define DECODE_OPERAND_REG_7(RegClass, OpWidth) \
+#define DECODE_OPERAND_SREG_7(RegClass, OpWidth) \
DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
+#define DECODE_OPERAND_SREG_8(RegClass, OpWidth) \
+ DECODE_SrcOp(Decode##RegClass##RegisterClass, 8, OpWidth, Imm, false, 0)
+
// Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
// Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC).
// Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
@@ -270,20 +273,21 @@ DECODE_OPERAND_REG_8(VReg_384)
DECODE_OPERAND_REG_8(VReg_512)
DECODE_OPERAND_REG_8(VReg_1024)
-DECODE_OPERAND_REG_7(SReg_32, OPW32)
-DECODE_OPERAND_REG_7(SReg_32_XM0, OPW32)
-DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32)
-DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32)
-DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32)
-DECODE_OPERAND_REG_7(SReg_64, OPW64)
-DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64)
-DECODE_OPERAND_REG_7(SReg_64_XEXEC_XNULL, OPW64)
-DECODE_OPERAND_REG_7(SReg_96, OPW96)
-DECODE_OPERAND_REG_7(SReg_128, OPW128)
-DECODE_OPERAND_REG_7(SReg_128_XNULL, OPW128)
-DECODE_OPERAND_REG_7(SReg_256, OPW256)
-DECODE_OPERAND_REG_7(SReg_256_XNULL, OPW256)
-DECODE_OPERAND_REG_7(SReg_512, OPW512)
+DECODE_OPERAND_SREG_7(SReg_32, OPW32)
+DECODE_OPERAND_SREG_7(SReg_32_XM0, OPW32)
+DECODE_OPERAND_SREG_7(SReg_32_XEXEC, OPW32)
+DECODE_OPERAND_SREG_7(SReg_32_XM0_XEXEC, OPW32)
+DECODE_OPERAND_SREG_7(SReg_32_XEXEC_HI, OPW32)
+DECODE_OPERAND_SREG_7(SReg_64_XEXEC, OPW64)
+DECODE_OPERAND_SREG_7(SReg_64_XEXEC_XNULL, OPW64)
+DECODE_OPERAND_SREG_7(SReg_96, OPW96)
+DECODE_OPERAND_SREG_7(SReg_128, OPW128)
+DECODE_OPERAND_SREG_7(SReg_128_XNULL, OPW128)
+DECODE_OPERAND_SREG_7(SReg_256, OPW256)
+DECODE_OPERAND_SREG_7(SReg_256_XNULL, OPW256)
+DECODE_OPERAND_SREG_7(SReg_512, OPW512)
+
+DECODE_OPERAND_SREG_8(SReg_64, OPW64)
DECODE_OPERAND_REG_8(AGPR_32)
DECODE_OPERAND_REG_8(AReg_64)
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt
index 291f348a35cc6..99a210b4ed088 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt
@@ -2548,6 +2548,9 @@
# GFX11: s_setpc_b64 vcc ; encoding: [0x6a,0x48,0x80,0xbe]
0x6a,0x48,0x80,0xbe
+# GFX11: s_setpc_b64 -11/*Invalid immediate*/ ; encoding: [0xf5,0x48,0x80,0xbe]
+0xcb,0x48,0xf5,0xbe
+
# GFX11: s_sext_i32_i16 exec_hi, s1 ; encoding: [0x01,0x0f,0xff,0xbe]
0x01,0x0f,0xff,0xbe
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
index fa7d020bdd726..90528a97fa1df 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
@@ -3267,6 +3267,9 @@
# GFX12: s_setpc_b64 vcc ; encoding: [0x6a,0x48,0x80,0xbe]
0x6a,0x48,0x80,0xbe
+# GFX12: s_setpc_b64 -11/*Invalid immediate*/ ; encoding: [0xf5,0x48,0x80,0xbe]
+0xcb,0x48,0xf5,0xbe
+
# GFX12: s_sext_i32_i16 exec_hi, s1 ; encoding: [0x01,0x0f,0xff,0xbe]
0x01,0x0f,0xff,0xbe
|
arsenm
approved these changes
Mar 7, 2025
| 0x6a,0x48,0x80,0xbe | ||
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| # GFX11: s_setpc_b64 -11/*Invalid immediate*/ ; encoding: [0xf5,0x48,0x80,0xbe] | ||
| 0xcb,0x48,0xf5,0xbe |
Contributor
There was a problem hiding this comment.
Maybe test with more operand bit widths? Or I guess only SReg_64 changed?
Collaborator
Author
There was a problem hiding this comment.
Yes, it's just SReg_64. I hope to have to time to check other cases more thoroughly, but we need this s_setpc fix as a matter of urgency.
Collaborator
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/10/builds/868 Here is the relevant piece of the build log for the reference |
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/33/builds/12645 Here is the relevant piece of the build log for the reference |
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These are encoded as 8-bit fields.