[Xtensa] Implement Xtensa Mul and Div Options. #132157
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@llvm/pr-subscribers-mc Author: Andrei Safronov (andreisfr) ChangesImplement Xtensa Mul16, Mul32, Mul32High and Div32 Options. Patch is 59.62 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/132157.diff 9 Files Affected:
diff --git a/llvm/lib/Target/Xtensa/XtensaFeatures.td b/llvm/lib/Target/Xtensa/XtensaFeatures.td
index 184828cd253f3..d2e0a711a3575 100644
--- a/llvm/lib/Target/Xtensa/XtensaFeatures.td
+++ b/llvm/lib/Target/Xtensa/XtensaFeatures.td
@@ -22,3 +22,23 @@ def FeatureBoolean : SubtargetFeature<"bool", "HasBoolean", "true",
"Enable Xtensa Boolean extension">;
def HasBoolean : Predicate<"Subtarget->hasBoolean()">,
AssemblerPredicate<(all_of FeatureBoolean)>;
+
+def FeatureMul16 : SubtargetFeature<"mul16", "HasMul16", "true",
+ "Enable Xtensa Mul16 option">;
+def HasMul16 : Predicate<"Subtarget->hasMul16()">,
+ AssemblerPredicate<(all_of FeatureMul16)>;
+
+def FeatureMul32 : SubtargetFeature<"mul32", "HasMul32", "true",
+ "Enable Xtensa Mul32 option">;
+def HasMul32 : Predicate<"Subtarget->hasMul32()">,
+ AssemblerPredicate<(all_of FeatureMul32)>;
+
+def FeatureMul32High : SubtargetFeature<"mul32high", "HasMul32High", "true",
+ "Enable Xtensa Mul32High option">;
+def HasMul32High : Predicate<"Subtarget->hasMul32High()">,
+ AssemblerPredicate<(all_of FeatureMul32High)>;
+
+def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true",
+ "Enable Xtensa Div32 option">;
+def HasDiv32 : Predicate<"Subtarget->hasDiv32()">,
+ AssemblerPredicate<(all_of FeatureDiv32)>;
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 57f0cbbc36c24..0b0e41c1c7b4e 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -106,16 +106,34 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
setCondCodeAction(ISD::SETUGT, MVT::i32, Expand);
setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
- setOperationAction(ISD::MUL, MVT::i32, Expand);
- setOperationAction(ISD::MULHU, MVT::i32, Expand);
- setOperationAction(ISD::MULHS, MVT::i32, Expand);
+ if (Subtarget.hasMul32())
+ setOperationAction(ISD::MUL, MVT::i32, Legal);
+ else
+ setOperationAction(ISD::MUL, MVT::i32, Expand);
+
+ if (Subtarget.hasMul32High()) {
+ setOperationAction(ISD::MULHU, MVT::i32, Legal);
+ setOperationAction(ISD::MULHS, MVT::i32, Legal);
+ } else {
+ setOperationAction(ISD::MULHU, MVT::i32, Expand);
+ setOperationAction(ISD::MULHS, MVT::i32, Expand);
+ }
+
setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
- setOperationAction(ISD::SDIV, MVT::i32, Expand);
- setOperationAction(ISD::UDIV, MVT::i32, Expand);
- setOperationAction(ISD::SREM, MVT::i32, Expand);
- setOperationAction(ISD::UREM, MVT::i32, Expand);
+ if (Subtarget.hasDiv32()) {
+ setOperationAction(ISD::SDIV, MVT::i32, Legal);
+ setOperationAction(ISD::UDIV, MVT::i32, Legal);
+ setOperationAction(ISD::SREM, MVT::i32, Legal);
+ setOperationAction(ISD::UREM, MVT::i32, Legal);
+ } else {
+ setOperationAction(ISD::SDIV, MVT::i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ }
+
setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index 1f397e3ecac35..23f2298b55c96 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -850,6 +850,36 @@ let Constraints = "$dr = $r,@earlyclobber $dr" in {
"movt\t$r, $s, $t", []>, Requires<[HasBoolean]>;
}
+//===----------------------------------------------------------------------===//
+// Mul16 Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasMul16] in {
+ def MUL16S : RRR_Inst<0x00, 0x01, 0x0D, (outs AR:$r), (ins AR:$s, AR:$t),
+ "mul16s\t$r, $s, $t", []>;
+ def MUL16U : RRR_Inst<0x00, 0x01, 0x0C, (outs AR:$r), (ins AR:$s, AR:$t),
+ "mul16u\t$r, $s, $t", []>;
+}
+
+//===----------------------------------------------------------------------===//
+// Mul32 Instructions
+//===----------------------------------------------------------------------===//
+
+def MULL : ArithLogic_RRR<0x08, 0x02, "mull", mul, 1>, Requires<[HasMul32]>;
+def MULUH : ArithLogic_RRR<0x0A, 0x02, "muluh", mulhu, 1>, Requires<[HasMul32High]>;
+def MULSH : ArithLogic_RRR<0x0B, 0x02, "mulsh", mulhs, 1>, Requires<[HasMul32High]>;
+
+//===----------------------------------------------------------------------===//
+// Div32 Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasDiv32] in {
+ def QUOS : ArithLogic_RRR<0x0D, 0x02, "quos", sdiv>;
+ def QUOU : ArithLogic_RRR<0x0C, 0x02, "quou", udiv>;
+ def REMS : ArithLogic_RRR<0x0F, 0x02, "rems", srem>;
+ def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>;
+}
+
//===----------------------------------------------------------------------===//
// DSP Instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
index 770f73905b337..3c3c49dd716df 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -66,6 +66,14 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
bool hasDensity() const { return HasDensity; }
+ bool hasMul16() const { return HasMul16; }
+
+ bool hasMul32() const { return HasMul32; }
+
+ bool hasMul32High() const { return HasMul32High; }
+
+ bool hasDiv32() const { return HasDiv32; }
+
bool hasMAC16() const { return HasMAC16; }
bool hasWindowed() const { return HasWindowed; }
diff --git a/llvm/test/CodeGen/Xtensa/div.ll b/llvm/test/CodeGen/Xtensa/div.ll
index 8d51c571efb4c..48630e3960b9a 100644
--- a/llvm/test/CodeGen/Xtensa/div.ll
+++ b/llvm/test/CodeGen/Xtensa/div.ll
@@ -1,10 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=XTENSA %s
+; RUN: llc -mtriple=xtensa -mattr=+div32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=XTENSA-DIV %s
define i32 @udiv(i32 %a, i32 %b) nounwind {
; XTENSA-LABEL: udiv:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: l32r a8, .LCPI0_0
@@ -13,13 +16,19 @@ define i32 @udiv(i32 %a, i32 %b) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: quou a2, a2, a3
+; XTENSA-DIV-NEXT: ret
%1 = udiv i32 %a, %b
ret i32 %1
}
define i32 @udiv_constant(i32 %a) nounwind {
; XTENSA-LABEL: udiv_constant:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: movi a3, 5
@@ -29,21 +38,34 @@ define i32 @udiv_constant(i32 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv_constant:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, 5
+; XTENSA-DIV-NEXT: quou a2, a2, a8
+; XTENSA-DIV-NEXT: ret
%1 = udiv i32 %a, 5
ret i32 %1
}
define i32 @udiv_pow2(i32 %a) nounwind {
; XTENSA-LABEL: udiv_pow2:
-; XTENSA: srli a2, a2, 3
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: srli a2, a2, 3
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv_pow2:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: srli a2, a2, 3
+; XTENSA-DIV-NEXT: ret
%1 = udiv i32 %a, 8
ret i32 %1
}
define i32 @udiv_constant_lhs(i32 %a) nounwind {
; XTENSA-LABEL: udiv_constant_lhs:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: or a3, a2, a2
@@ -54,13 +76,20 @@ define i32 @udiv_constant_lhs(i32 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv_constant_lhs:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, 10
+; XTENSA-DIV-NEXT: quou a2, a8, a2
+; XTENSA-DIV-NEXT: ret
%1 = udiv i32 10, %a
ret i32 %1
}
define i64 @udiv64(i64 %a, i64 %b) nounwind {
; XTENSA-LABEL: udiv64:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: l32r a8, .LCPI4_0
@@ -69,13 +98,26 @@ define i64 @udiv64(i64 %a, i64 %b) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv64:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: addi a8, a1, -16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
+; XTENSA-DIV-NEXT: l32r a8, .LCPI4_0
+; XTENSA-DIV-NEXT: callx0 a8
+; XTENSA-DIV-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload
+; XTENSA-DIV-NEXT: addi a8, a1, 16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: ret
%1 = udiv i64 %a, %b
ret i64 %1
}
define i64 @udiv64_constant(i64 %a) nounwind {
; XTENSA-LABEL: udiv64_constant:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: movi a4, 5
@@ -86,13 +128,28 @@ define i64 @udiv64_constant(i64 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv64_constant:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: addi a8, a1, -16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
+; XTENSA-DIV-NEXT: movi a4, 5
+; XTENSA-DIV-NEXT: movi a5, 0
+; XTENSA-DIV-NEXT: l32r a8, .LCPI5_0
+; XTENSA-DIV-NEXT: callx0 a8
+; XTENSA-DIV-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload
+; XTENSA-DIV-NEXT: addi a8, a1, 16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: ret
%1 = udiv i64 %a, 5
ret i64 %1
}
define i64 @udiv64_constant_lhs(i64 %a) nounwind {
; XTENSA-LABEL: udiv64_constant_lhs:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: or a5, a3, a3
@@ -105,13 +162,30 @@ define i64 @udiv64_constant_lhs(i64 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv64_constant_lhs:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: addi a8, a1, -16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
+; XTENSA-DIV-NEXT: or a5, a3, a3
+; XTENSA-DIV-NEXT: or a4, a2, a2
+; XTENSA-DIV-NEXT: movi a2, 10
+; XTENSA-DIV-NEXT: movi a3, 0
+; XTENSA-DIV-NEXT: l32r a8, .LCPI6_0
+; XTENSA-DIV-NEXT: callx0 a8
+; XTENSA-DIV-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload
+; XTENSA-DIV-NEXT: addi a8, a1, 16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: ret
%1 = udiv i64 10, %a
ret i64 %1
}
define i8 @udiv8(i8 %a, i8 %b) nounwind {
; XTENSA-LABEL: udiv8:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: movi a8, 255
@@ -123,13 +197,22 @@ define i8 @udiv8(i8 %a, i8 %b) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv8:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, 255
+; XTENSA-DIV-NEXT: and a9, a3, a8
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: quou a2, a8, a9
+; XTENSA-DIV-NEXT: ret
%1 = udiv i8 %a, %b
ret i8 %1
}
define i8 @udiv8_constant(i8 %a) nounwind {
; XTENSA-LABEL: udiv8_constant:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: movi a8, 255
@@ -141,23 +224,40 @@ define i8 @udiv8_constant(i8 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv8_constant:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, 255
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: movi a9, 5
+; XTENSA-DIV-NEXT: quou a2, a8, a9
+; XTENSA-DIV-NEXT: ret
%1 = udiv i8 %a, 5
ret i8 %1
}
define i8 @udiv8_pow2(i8 %a) nounwind {
; XTENSA-LABEL: udiv8_pow2:
-; XTENSA: movi a8, 248
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: movi a8, 248
; XTENSA-NEXT: and a8, a2, a8
; XTENSA-NEXT: srli a2, a8, 3
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv8_pow2:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, 248
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: srli a2, a8, 3
+; XTENSA-DIV-NEXT: ret
%1 = udiv i8 %a, 8
ret i8 %1
}
define i8 @udiv8_constant_lhs(i8 %a) nounwind {
; XTENSA-LABEL: udiv8_constant_lhs:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: movi a8, 255
@@ -169,13 +269,22 @@ define i8 @udiv8_constant_lhs(i8 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv8_constant_lhs:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, 255
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: movi a9, 10
+; XTENSA-DIV-NEXT: quou a2, a9, a8
+; XTENSA-DIV-NEXT: ret
%1 = udiv i8 10, %a
ret i8 %1
}
define i16 @udiv16(i16 %a, i16 %b) nounwind {
; XTENSA-LABEL: udiv16:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: l32r a8, .LCPI11_0
@@ -187,13 +296,22 @@ define i16 @udiv16(i16 %a, i16 %b) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv16:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: l32r a8, .LCPI11_0
+; XTENSA-DIV-NEXT: and a9, a3, a8
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: quou a2, a8, a9
+; XTENSA-DIV-NEXT: ret
%1 = udiv i16 %a, %b
ret i16 %1
}
define i16 @udiv16_constant(i16 %a) nounwind {
; XTENSA-LABEL: udiv16_constant:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: l32r a8, .LCPI12_0
@@ -205,23 +323,40 @@ define i16 @udiv16_constant(i16 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv16_constant:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: l32r a8, .LCPI12_0
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: movi a9, 5
+; XTENSA-DIV-NEXT: quou a2, a8, a9
+; XTENSA-DIV-NEXT: ret
%1 = udiv i16 %a, 5
ret i16 %1
}
define i16 @udiv16_pow2(i16 %a) nounwind {
; XTENSA-LABEL: udiv16_pow2:
-; XTENSA: l32r a8, .LCPI13_0
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: l32r a8, .LCPI13_0
; XTENSA-NEXT: and a8, a2, a8
; XTENSA-NEXT: srli a2, a8, 3
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv16_pow2:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: l32r a8, .LCPI13_0
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: srli a2, a8, 3
+; XTENSA-DIV-NEXT: ret
%1 = udiv i16 %a, 8
ret i16 %1
}
define i32 @sdiv(i32 %a, i32 %b) nounwind {
; XTENSA-LABEL: sdiv:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: l32r a8, .LCPI14_0
@@ -230,13 +365,19 @@ define i32 @sdiv(i32 %a, i32 %b) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: sdiv:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: quos a2, a2, a3
+; XTENSA-DIV-NEXT: ret
%1 = sdiv i32 %a, %b
ret i32 %1
}
define i32 @sdiv_constant_lhs(i32 %a) nounwind {
; XTENSA-LABEL: sdiv_constant_lhs:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: or a3, a2, a2
@@ -247,13 +388,20 @@ define i32 @sdiv_constant_lhs(i32 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: sdiv_constant_lhs:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, -10
+; XTENSA-DIV-NEXT: quos a2, a8, a2
+; XTENSA-DIV-NEXT: ret
%1 = sdiv i32 -10, %a
ret i32 %1
}
define i64 @sdiv64(i64 %a, i64 %b) nounwind {
; XTENSA-LABEL: sdiv64:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: l32r a8, .LCPI16_0
@@ -262,13 +410,26 @@ define i64 @sdiv64(i64 %a, i64 %b) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: sdiv64:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: addi a8, a1, -16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
+; XTENSA-DIV-NEXT: l32r a8, .LCPI16_0
+; XTENSA-DIV-NEXT: callx0 a8
+; XTENSA-DIV-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload
+; XTENSA-DIV-NEXT: addi a8, a1, 16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: ret
%1 = sdiv i64 %a, %b
ret i64 %1
}
define i64 @sdiv64_constant(i64 %a) nounwind {
; XTENSA-LABEL: sdiv64_constant:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: movi a4, 5
@@ -279,13 +440,28 @@ define i64 @sdiv64_constant(i64 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: sdiv64_constant:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: addi a8, a1, -16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
+; XTENSA-DIV-NEXT: movi a4, 5
+; XTENSA-DIV-NEXT: movi a5, 0
+; XTENSA-DIV-NEXT: l32r a8, .LCPI17_0
+; XTENSA-DIV-NEXT: callx0 a8
+; XTENSA-DIV-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload
+; XTENSA-DIV-NEXT: addi a8, a1, 16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: ret
%1 = sdiv i64 %a, 5
ret i64 %1
}
define i64 @sdiv64_constant_lhs(i64 %a) nounwind {
; XTENSA-LABEL: sdiv64_constant_lhs:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; ...
[truncated]
|
Member
|
@llvm/pr-subscribers-backend-xtensa Author: Andrei Safronov (andreisfr) ChangesImplement Xtensa Mul16, Mul32, Mul32High and Div32 Options. Patch is 59.62 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/132157.diff 9 Files Affected:
diff --git a/llvm/lib/Target/Xtensa/XtensaFeatures.td b/llvm/lib/Target/Xtensa/XtensaFeatures.td
index 184828cd253f3..d2e0a711a3575 100644
--- a/llvm/lib/Target/Xtensa/XtensaFeatures.td
+++ b/llvm/lib/Target/Xtensa/XtensaFeatures.td
@@ -22,3 +22,23 @@ def FeatureBoolean : SubtargetFeature<"bool", "HasBoolean", "true",
"Enable Xtensa Boolean extension">;
def HasBoolean : Predicate<"Subtarget->hasBoolean()">,
AssemblerPredicate<(all_of FeatureBoolean)>;
+
+def FeatureMul16 : SubtargetFeature<"mul16", "HasMul16", "true",
+ "Enable Xtensa Mul16 option">;
+def HasMul16 : Predicate<"Subtarget->hasMul16()">,
+ AssemblerPredicate<(all_of FeatureMul16)>;
+
+def FeatureMul32 : SubtargetFeature<"mul32", "HasMul32", "true",
+ "Enable Xtensa Mul32 option">;
+def HasMul32 : Predicate<"Subtarget->hasMul32()">,
+ AssemblerPredicate<(all_of FeatureMul32)>;
+
+def FeatureMul32High : SubtargetFeature<"mul32high", "HasMul32High", "true",
+ "Enable Xtensa Mul32High option">;
+def HasMul32High : Predicate<"Subtarget->hasMul32High()">,
+ AssemblerPredicate<(all_of FeatureMul32High)>;
+
+def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true",
+ "Enable Xtensa Div32 option">;
+def HasDiv32 : Predicate<"Subtarget->hasDiv32()">,
+ AssemblerPredicate<(all_of FeatureDiv32)>;
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 57f0cbbc36c24..0b0e41c1c7b4e 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -106,16 +106,34 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
setCondCodeAction(ISD::SETUGT, MVT::i32, Expand);
setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
- setOperationAction(ISD::MUL, MVT::i32, Expand);
- setOperationAction(ISD::MULHU, MVT::i32, Expand);
- setOperationAction(ISD::MULHS, MVT::i32, Expand);
+ if (Subtarget.hasMul32())
+ setOperationAction(ISD::MUL, MVT::i32, Legal);
+ else
+ setOperationAction(ISD::MUL, MVT::i32, Expand);
+
+ if (Subtarget.hasMul32High()) {
+ setOperationAction(ISD::MULHU, MVT::i32, Legal);
+ setOperationAction(ISD::MULHS, MVT::i32, Legal);
+ } else {
+ setOperationAction(ISD::MULHU, MVT::i32, Expand);
+ setOperationAction(ISD::MULHS, MVT::i32, Expand);
+ }
+
setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
- setOperationAction(ISD::SDIV, MVT::i32, Expand);
- setOperationAction(ISD::UDIV, MVT::i32, Expand);
- setOperationAction(ISD::SREM, MVT::i32, Expand);
- setOperationAction(ISD::UREM, MVT::i32, Expand);
+ if (Subtarget.hasDiv32()) {
+ setOperationAction(ISD::SDIV, MVT::i32, Legal);
+ setOperationAction(ISD::UDIV, MVT::i32, Legal);
+ setOperationAction(ISD::SREM, MVT::i32, Legal);
+ setOperationAction(ISD::UREM, MVT::i32, Legal);
+ } else {
+ setOperationAction(ISD::SDIV, MVT::i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ }
+
setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index 1f397e3ecac35..23f2298b55c96 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -850,6 +850,36 @@ let Constraints = "$dr = $r,@earlyclobber $dr" in {
"movt\t$r, $s, $t", []>, Requires<[HasBoolean]>;
}
+//===----------------------------------------------------------------------===//
+// Mul16 Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasMul16] in {
+ def MUL16S : RRR_Inst<0x00, 0x01, 0x0D, (outs AR:$r), (ins AR:$s, AR:$t),
+ "mul16s\t$r, $s, $t", []>;
+ def MUL16U : RRR_Inst<0x00, 0x01, 0x0C, (outs AR:$r), (ins AR:$s, AR:$t),
+ "mul16u\t$r, $s, $t", []>;
+}
+
+//===----------------------------------------------------------------------===//
+// Mul32 Instructions
+//===----------------------------------------------------------------------===//
+
+def MULL : ArithLogic_RRR<0x08, 0x02, "mull", mul, 1>, Requires<[HasMul32]>;
+def MULUH : ArithLogic_RRR<0x0A, 0x02, "muluh", mulhu, 1>, Requires<[HasMul32High]>;
+def MULSH : ArithLogic_RRR<0x0B, 0x02, "mulsh", mulhs, 1>, Requires<[HasMul32High]>;
+
+//===----------------------------------------------------------------------===//
+// Div32 Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasDiv32] in {
+ def QUOS : ArithLogic_RRR<0x0D, 0x02, "quos", sdiv>;
+ def QUOU : ArithLogic_RRR<0x0C, 0x02, "quou", udiv>;
+ def REMS : ArithLogic_RRR<0x0F, 0x02, "rems", srem>;
+ def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>;
+}
+
//===----------------------------------------------------------------------===//
// DSP Instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
index 770f73905b337..3c3c49dd716df 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -66,6 +66,14 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
bool hasDensity() const { return HasDensity; }
+ bool hasMul16() const { return HasMul16; }
+
+ bool hasMul32() const { return HasMul32; }
+
+ bool hasMul32High() const { return HasMul32High; }
+
+ bool hasDiv32() const { return HasDiv32; }
+
bool hasMAC16() const { return HasMAC16; }
bool hasWindowed() const { return HasWindowed; }
diff --git a/llvm/test/CodeGen/Xtensa/div.ll b/llvm/test/CodeGen/Xtensa/div.ll
index 8d51c571efb4c..48630e3960b9a 100644
--- a/llvm/test/CodeGen/Xtensa/div.ll
+++ b/llvm/test/CodeGen/Xtensa/div.ll
@@ -1,10 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=XTENSA %s
+; RUN: llc -mtriple=xtensa -mattr=+div32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=XTENSA-DIV %s
define i32 @udiv(i32 %a, i32 %b) nounwind {
; XTENSA-LABEL: udiv:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: l32r a8, .LCPI0_0
@@ -13,13 +16,19 @@ define i32 @udiv(i32 %a, i32 %b) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: quou a2, a2, a3
+; XTENSA-DIV-NEXT: ret
%1 = udiv i32 %a, %b
ret i32 %1
}
define i32 @udiv_constant(i32 %a) nounwind {
; XTENSA-LABEL: udiv_constant:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: movi a3, 5
@@ -29,21 +38,34 @@ define i32 @udiv_constant(i32 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv_constant:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, 5
+; XTENSA-DIV-NEXT: quou a2, a2, a8
+; XTENSA-DIV-NEXT: ret
%1 = udiv i32 %a, 5
ret i32 %1
}
define i32 @udiv_pow2(i32 %a) nounwind {
; XTENSA-LABEL: udiv_pow2:
-; XTENSA: srli a2, a2, 3
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: srli a2, a2, 3
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv_pow2:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: srli a2, a2, 3
+; XTENSA-DIV-NEXT: ret
%1 = udiv i32 %a, 8
ret i32 %1
}
define i32 @udiv_constant_lhs(i32 %a) nounwind {
; XTENSA-LABEL: udiv_constant_lhs:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: or a3, a2, a2
@@ -54,13 +76,20 @@ define i32 @udiv_constant_lhs(i32 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv_constant_lhs:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, 10
+; XTENSA-DIV-NEXT: quou a2, a8, a2
+; XTENSA-DIV-NEXT: ret
%1 = udiv i32 10, %a
ret i32 %1
}
define i64 @udiv64(i64 %a, i64 %b) nounwind {
; XTENSA-LABEL: udiv64:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: l32r a8, .LCPI4_0
@@ -69,13 +98,26 @@ define i64 @udiv64(i64 %a, i64 %b) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv64:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: addi a8, a1, -16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
+; XTENSA-DIV-NEXT: l32r a8, .LCPI4_0
+; XTENSA-DIV-NEXT: callx0 a8
+; XTENSA-DIV-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload
+; XTENSA-DIV-NEXT: addi a8, a1, 16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: ret
%1 = udiv i64 %a, %b
ret i64 %1
}
define i64 @udiv64_constant(i64 %a) nounwind {
; XTENSA-LABEL: udiv64_constant:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: movi a4, 5
@@ -86,13 +128,28 @@ define i64 @udiv64_constant(i64 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv64_constant:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: addi a8, a1, -16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
+; XTENSA-DIV-NEXT: movi a4, 5
+; XTENSA-DIV-NEXT: movi a5, 0
+; XTENSA-DIV-NEXT: l32r a8, .LCPI5_0
+; XTENSA-DIV-NEXT: callx0 a8
+; XTENSA-DIV-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload
+; XTENSA-DIV-NEXT: addi a8, a1, 16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: ret
%1 = udiv i64 %a, 5
ret i64 %1
}
define i64 @udiv64_constant_lhs(i64 %a) nounwind {
; XTENSA-LABEL: udiv64_constant_lhs:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: or a5, a3, a3
@@ -105,13 +162,30 @@ define i64 @udiv64_constant_lhs(i64 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv64_constant_lhs:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: addi a8, a1, -16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
+; XTENSA-DIV-NEXT: or a5, a3, a3
+; XTENSA-DIV-NEXT: or a4, a2, a2
+; XTENSA-DIV-NEXT: movi a2, 10
+; XTENSA-DIV-NEXT: movi a3, 0
+; XTENSA-DIV-NEXT: l32r a8, .LCPI6_0
+; XTENSA-DIV-NEXT: callx0 a8
+; XTENSA-DIV-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload
+; XTENSA-DIV-NEXT: addi a8, a1, 16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: ret
%1 = udiv i64 10, %a
ret i64 %1
}
define i8 @udiv8(i8 %a, i8 %b) nounwind {
; XTENSA-LABEL: udiv8:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: movi a8, 255
@@ -123,13 +197,22 @@ define i8 @udiv8(i8 %a, i8 %b) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv8:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, 255
+; XTENSA-DIV-NEXT: and a9, a3, a8
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: quou a2, a8, a9
+; XTENSA-DIV-NEXT: ret
%1 = udiv i8 %a, %b
ret i8 %1
}
define i8 @udiv8_constant(i8 %a) nounwind {
; XTENSA-LABEL: udiv8_constant:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: movi a8, 255
@@ -141,23 +224,40 @@ define i8 @udiv8_constant(i8 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv8_constant:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, 255
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: movi a9, 5
+; XTENSA-DIV-NEXT: quou a2, a8, a9
+; XTENSA-DIV-NEXT: ret
%1 = udiv i8 %a, 5
ret i8 %1
}
define i8 @udiv8_pow2(i8 %a) nounwind {
; XTENSA-LABEL: udiv8_pow2:
-; XTENSA: movi a8, 248
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: movi a8, 248
; XTENSA-NEXT: and a8, a2, a8
; XTENSA-NEXT: srli a2, a8, 3
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv8_pow2:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, 248
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: srli a2, a8, 3
+; XTENSA-DIV-NEXT: ret
%1 = udiv i8 %a, 8
ret i8 %1
}
define i8 @udiv8_constant_lhs(i8 %a) nounwind {
; XTENSA-LABEL: udiv8_constant_lhs:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: movi a8, 255
@@ -169,13 +269,22 @@ define i8 @udiv8_constant_lhs(i8 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv8_constant_lhs:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, 255
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: movi a9, 10
+; XTENSA-DIV-NEXT: quou a2, a9, a8
+; XTENSA-DIV-NEXT: ret
%1 = udiv i8 10, %a
ret i8 %1
}
define i16 @udiv16(i16 %a, i16 %b) nounwind {
; XTENSA-LABEL: udiv16:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: l32r a8, .LCPI11_0
@@ -187,13 +296,22 @@ define i16 @udiv16(i16 %a, i16 %b) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv16:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: l32r a8, .LCPI11_0
+; XTENSA-DIV-NEXT: and a9, a3, a8
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: quou a2, a8, a9
+; XTENSA-DIV-NEXT: ret
%1 = udiv i16 %a, %b
ret i16 %1
}
define i16 @udiv16_constant(i16 %a) nounwind {
; XTENSA-LABEL: udiv16_constant:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: l32r a8, .LCPI12_0
@@ -205,23 +323,40 @@ define i16 @udiv16_constant(i16 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv16_constant:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: l32r a8, .LCPI12_0
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: movi a9, 5
+; XTENSA-DIV-NEXT: quou a2, a8, a9
+; XTENSA-DIV-NEXT: ret
%1 = udiv i16 %a, 5
ret i16 %1
}
define i16 @udiv16_pow2(i16 %a) nounwind {
; XTENSA-LABEL: udiv16_pow2:
-; XTENSA: l32r a8, .LCPI13_0
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: l32r a8, .LCPI13_0
; XTENSA-NEXT: and a8, a2, a8
; XTENSA-NEXT: srli a2, a8, 3
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: udiv16_pow2:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: l32r a8, .LCPI13_0
+; XTENSA-DIV-NEXT: and a8, a2, a8
+; XTENSA-DIV-NEXT: srli a2, a8, 3
+; XTENSA-DIV-NEXT: ret
%1 = udiv i16 %a, 8
ret i16 %1
}
define i32 @sdiv(i32 %a, i32 %b) nounwind {
; XTENSA-LABEL: sdiv:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: l32r a8, .LCPI14_0
@@ -230,13 +365,19 @@ define i32 @sdiv(i32 %a, i32 %b) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: sdiv:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: quos a2, a2, a3
+; XTENSA-DIV-NEXT: ret
%1 = sdiv i32 %a, %b
ret i32 %1
}
define i32 @sdiv_constant_lhs(i32 %a) nounwind {
; XTENSA-LABEL: sdiv_constant_lhs:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: or a3, a2, a2
@@ -247,13 +388,20 @@ define i32 @sdiv_constant_lhs(i32 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: sdiv_constant_lhs:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: movi a8, -10
+; XTENSA-DIV-NEXT: quos a2, a8, a2
+; XTENSA-DIV-NEXT: ret
%1 = sdiv i32 -10, %a
ret i32 %1
}
define i64 @sdiv64(i64 %a, i64 %b) nounwind {
; XTENSA-LABEL: sdiv64:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: l32r a8, .LCPI16_0
@@ -262,13 +410,26 @@ define i64 @sdiv64(i64 %a, i64 %b) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: sdiv64:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: addi a8, a1, -16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
+; XTENSA-DIV-NEXT: l32r a8, .LCPI16_0
+; XTENSA-DIV-NEXT: callx0 a8
+; XTENSA-DIV-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload
+; XTENSA-DIV-NEXT: addi a8, a1, 16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: ret
%1 = sdiv i64 %a, %b
ret i64 %1
}
define i64 @sdiv64_constant(i64 %a) nounwind {
; XTENSA-LABEL: sdiv64_constant:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT: movi a4, 5
@@ -279,13 +440,28 @@ define i64 @sdiv64_constant(i64 %a) nounwind {
; XTENSA-NEXT: addi a8, a1, 16
; XTENSA-NEXT: or a1, a8, a8
; XTENSA-NEXT: ret
+;
+; XTENSA-DIV-LABEL: sdiv64_constant:
+; XTENSA-DIV: # %bb.0:
+; XTENSA-DIV-NEXT: addi a8, a1, -16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill
+; XTENSA-DIV-NEXT: movi a4, 5
+; XTENSA-DIV-NEXT: movi a5, 0
+; XTENSA-DIV-NEXT: l32r a8, .LCPI17_0
+; XTENSA-DIV-NEXT: callx0 a8
+; XTENSA-DIV-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload
+; XTENSA-DIV-NEXT: addi a8, a1, 16
+; XTENSA-DIV-NEXT: or a1, a8, a8
+; XTENSA-DIV-NEXT: ret
%1 = sdiv i64 %a, 5
ret i64 %1
}
define i64 @sdiv64_constant_lhs(i64 %a) nounwind {
; XTENSA-LABEL: sdiv64_constant_lhs:
-; XTENSA: addi a8, a1, -16
+; XTENSA: # %bb.0:
+; XTENSA-NEXT: addi a8, a1, -16
; ...
[truncated]
|
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MaskRay
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Apr 7, 2025
llvm/test/CodeGen/Xtensa/div.ll
Outdated
| ; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \ | ||
| ; RUN: | FileCheck -check-prefix=XTENSA %s | ||
| ; RUN: llc -mtriple=xtensa -mattr=+div32 -verify-machineinstrs < %s \ | ||
| ; RUN: | FileCheck -check-prefix=XTENSA-DIV %s |
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Indent continulation lines by 2 spaces
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Thank you very much for comments. I rebased current version on main branch to resolve conflicts and fixed indent.
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Also I fixed "callw.ll" test, because code generation changed a bit in main branch.
| } | ||
|
|
||
| bool hasDensity() const { return HasDensity; } | ||
|
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I think it's not necessary to add a blank line between all the trivial functions.
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arsenm
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Implement Xtensa Mul16, Mul32, Mul32High and Div32 Options. Also fix callw test.
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/59/builds/16281 Here is the relevant piece of the build log for the reference |
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Implement Xtensa Mul16, Mul32, Mul32High and Div32 Options. Also fix callw test.
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Implement Xtensa Mul16, Mul32, Mul32High and Div32 Options.