[Xtensa] Implement Xtensa Mul and Div Options.

llvm/lib/Target/Xtensa/XtensaFeatures.td

@@ -47,3 +47,23 @@ def FeatureMINMAX : SubtargetFeature<"minmax", "HasMINMAX", "true",
                                      "Enable Xtensa MINMAX option">;
 def HasMINMAX : Predicate<"Subtarget->hasMINMAX()">,
                 AssemblerPredicate<(all_of FeatureMINMAX)>;
+
+def FeatureMul16 : SubtargetFeature<"mul16", "HasMul16", "true",
+                                    "Enable Xtensa Mul16 option">;
+def HasMul16 : Predicate<"Subtarget->hasMul16()">,
+               AssemblerPredicate<(all_of FeatureMul16)>;
+
+def FeatureMul32 : SubtargetFeature<"mul32", "HasMul32", "true",
+                                    "Enable Xtensa Mul32 option">;
+def HasMul32 : Predicate<"Subtarget->hasMul32()">,
+               AssemblerPredicate<(all_of FeatureMul32)>;
+
+def FeatureMul32High : SubtargetFeature<"mul32high", "HasMul32High", "true",
+                                        "Enable Xtensa Mul32High option">;
+def HasMul32High : Predicate<"Subtarget->hasMul32High()">,
+                   AssemblerPredicate<(all_of FeatureMul32High)>;
+
+def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true",
+                                    "Enable Xtensa Div32 option">;
+def HasDiv32 : Predicate<"Subtarget->hasDiv32()">,
+               AssemblerPredicate<(all_of FeatureDiv32)>;

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

@@ -115,16 +115,34 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
   setCondCodeAction(ISD::SETUGT, MVT::i32, Expand);
   setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
 
-  setOperationAction(ISD::MUL, MVT::i32, Expand);
-  setOperationAction(ISD::MULHU, MVT::i32, Expand);
-  setOperationAction(ISD::MULHS, MVT::i32, Expand);
+  if (Subtarget.hasMul32())
+    setOperationAction(ISD::MUL, MVT::i32, Legal);
+  else
+    setOperationAction(ISD::MUL, MVT::i32, Expand);
+
+  if (Subtarget.hasMul32High()) {
+    setOperationAction(ISD::MULHU, MVT::i32, Legal);
+    setOperationAction(ISD::MULHS, MVT::i32, Legal);
+  } else {
+    setOperationAction(ISD::MULHU, MVT::i32, Expand);
+    setOperationAction(ISD::MULHS, MVT::i32, Expand);
+  }
+
   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
   setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
 
-  setOperationAction(ISD::SDIV, MVT::i32, Expand);
-  setOperationAction(ISD::UDIV, MVT::i32, Expand);
-  setOperationAction(ISD::SREM, MVT::i32, Expand);
-  setOperationAction(ISD::UREM, MVT::i32, Expand);
+  if (Subtarget.hasDiv32()) {
+    setOperationAction(ISD::SDIV, MVT::i32, Legal);
+    setOperationAction(ISD::UDIV, MVT::i32, Legal);
+    setOperationAction(ISD::SREM, MVT::i32, Legal);
+    setOperationAction(ISD::UREM, MVT::i32, Legal);
+  } else {
+    setOperationAction(ISD::SDIV, MVT::i32, Expand);
+    setOperationAction(ISD::UDIV, MVT::i32, Expand);
+    setOperationAction(ISD::SREM, MVT::i32, Expand);
+    setOperationAction(ISD::UREM, MVT::i32, Expand);
+  }
+
   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
 

llvm/lib/Target/Xtensa/XtensaInstrInfo.td

@@ -956,6 +956,36 @@ def LOOPNEZ : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target),
 
 def : InstAlias<"_loopnez\t$s, $target", (LOOPNEZ AR:$s, ltarget:$target)>;
 
+//===----------------------------------------------------------------------===//
+// Mul16 Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasMul16] in {
+  def MUL16S : RRR_Inst<0x00, 0x01, 0x0D, (outs AR:$r), (ins AR:$s, AR:$t),
+                       "mul16s\t$r, $s, $t", []>;
+  def MUL16U : RRR_Inst<0x00, 0x01, 0x0C, (outs AR:$r), (ins AR:$s, AR:$t),
+                       "mul16u\t$r, $s, $t", []>;
+}
+
+//===----------------------------------------------------------------------===//
+// Mul32 Instructions
+//===----------------------------------------------------------------------===//
+
+def MULL  : ArithLogic_RRR<0x08, 0x02, "mull", mul, 1>, Requires<[HasMul32]>;
+def MULUH : ArithLogic_RRR<0x0A, 0x02, "muluh", mulhu, 1>, Requires<[HasMul32High]>;
+def MULSH : ArithLogic_RRR<0x0B, 0x02, "mulsh", mulhs, 1>, Requires<[HasMul32High]>;
+
+//===----------------------------------------------------------------------===//
+// Div32 Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasDiv32] in {
+  def QUOS : ArithLogic_RRR<0x0D, 0x02, "quos", sdiv>;
+  def QUOU : ArithLogic_RRR<0x0C, 0x02, "quou", udiv>;
+  def REMS : ArithLogic_RRR<0x0F, 0x02, "rems", srem>;
+  def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>;
+}
+
 //===----------------------------------------------------------------------===//
 // DSP Instructions
 //===----------------------------------------------------------------------===//

llvm/lib/Target/Xtensa/XtensaSubtarget.h

@@ -73,6 +73,10 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
   bool hasCLAMPS() const { return HasCLAMPS; }
   bool hasNSA() const { return HasNSA; }
   bool hasMINMAX() const { return HasMINMAX; }
+  bool hasMul16() const { return HasMul16; }
+  bool hasMul32() const { return HasMul32; }
+  bool hasMul32High() const { return HasMul32High; }
+  bool hasDiv32() const { return HasDiv32; }
   bool isWindowedABI() const { return hasWindowed(); }
 
   // Automatically generated by tblgen.

llvm/test/CodeGen/Xtensa/callw.ll

@@ -7,8 +7,8 @@ define i32 @test_call_external(i32 %a) nounwind {
 ; CHECK-LABEL: test_call_external:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    entry a1, 32
-; CHECK-NEXT:    l32r a8, .LCPI0_0
 ; CHECK-NEXT:    or a10, a2, a2
+; CHECK-NEXT:    l32r a8, .LCPI0_0
 ; CHECK-NEXT:    callx8 a8
 ; CHECK-NEXT:    or a2, a10, a10
 ; CHECK-NEXT:    retw
@@ -30,8 +30,8 @@ define i32 @test_call_defined(i32 %a) nounwind {
 ; CHECK-LABEL: test_call_defined:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    entry a1, 32
-; CHECK-NEXT:    l32r a8, .LCPI2_0
 ; CHECK-NEXT:    or a10, a2, a2
+; CHECK-NEXT:    l32r a8, .LCPI2_0
 ; CHECK-NEXT:    callx8 a8
 ; CHECK-NEXT:    or a2, a10, a10
 ; CHECK-NEXT:    retw