[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension #132184
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This extension adds nine instructions, eight for non-memory-mapped devices synchronization and delay instruction. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Change-Id: I0472a9b3cd999f0b7d16aa351215cce12a788569
Change-Id: I3c0805af64e4513760f02e857887c93653a61d50
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@llvm/pr-subscribers-clang @llvm/pr-subscribers-clang-driver Author: quic_hchandel (hchandel) ChangesThis extension adds nine instructions, eight for non-memory-mapped devices synchronization and delay instruction. The current spec can be found at: This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <[email protected]> Patch is 21.65 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/132184.diff 14 Files Affected:
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 40b8eb6217240..74ceb24548b9c 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -212,6 +212,7 @@
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
// CHECK-NEXT: xqcisim 0.2 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+// CHECK-NEXT: xqcisync 0.2 'Xqcisync' (Qualcomm uC Sync Delay Extension)
// CHECK-NEXT: xrivosvisni 0.1 'XRivosVisni' (Rivos Vector Integer Small New)
// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)
// CHECK-EMPTY:
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 28d09cffa95c0..701296226e07f 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -482,6 +482,9 @@ The current vendor extensions supported are:
``experimental-Xqcisls``
LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
+``experimental-Xqcisync``
+ LLVM implements `version 0.2 of the Qualcomm uC Sync Delay extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
+
``Xmipscmove``
LLVM implements conditional move for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 205c2ad25f23e..8d3c93d389b49 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -130,6 +130,8 @@ Changes to the RISC-V Backend
* Added non-quadratic ``log-vrgather`` cost model for ``vrgather.vv`` instruction
* Adds experimental assembler support for the Qualcomm uC 'Xqcisim` (Simulation Hint)
extension.
+* Adds experimental assembler support for the Qualcomm uC 'Xqcisync` (Sync Delay)
+ extension.
* Adds assembler support for the 'Zilsd` (Load/Store Pair Instructions)
extension.
* Adds assembler support for the 'Zclsd` (Compressed Load/Store Pair Instructions)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index d3500e3e44c50..91e211f335e3f 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -772,6 +772,18 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_None;
}
+ bool isUImm5Slist() const {
+ if (!isImm())
+ return false;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_None;
+ int64_t Imm;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ return IsConstantImm &&
+ ((Imm == 0) || (Imm == 1) || (Imm == 2) || (Imm == 4) ||
+ (Imm == 8) || (Imm == 16) || (Imm == 15) || (Imm == 31)) &&
+ VK == RISCVMCExpr::VK_None;
+ }
+
bool isUImm8GE32() const {
int64_t Imm;
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_None;
@@ -1655,6 +1667,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5));
case Match_InvalidUImm5GE6Plus1:
return generateImmOutOfRangeError(Operands, ErrorInfo, 6, (1 << 5));
+ case Match_InvalidUImm5Slist:
+ return generateImmOutOfRangeError(
+ Operands, ErrorInfo, 0, (1 << 5) - 1,
+ "immediate must be one of: 0, 1, 2, 4, 8, 15, 16, 31 in the range ");
case Match_InvalidUImm6:
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
case Match_InvalidUImm7:
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 5abf15a404dfb..93cbf662bfa32 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -370,6 +370,15 @@ static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm,
return MCDisassembler::Success;
}
+static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm,
+ int64_t Address,
+ const MCDisassembler *Decoder) {
+ assert(isUInt<3>(Imm) && "Invalid Slist immediate");
+ const uint8_t Slist[] = {0, 1, 2, 4, 8, 16, 15, 31};
+ Inst.addOperand(MCOperand::createImm(Slist[Imm]));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
int64_t Address,
const MCDisassembler *Decoder) {
@@ -663,14 +672,15 @@ static constexpr FeatureBitset XRivosFeatureGroup = {
};
static constexpr FeatureBitset XqciFeatureGroup = {
- RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
- RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
- RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
- RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
- RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb,
- RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia,
- RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm,
- RISCV::FeatureVendorXqcisim, RISCV::FeatureVendorXqcisls,
+ RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
+ RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
+ RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
+ RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
+ RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb,
+ RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia,
+ RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm,
+ RISCV::FeatureVendorXqcisim, RISCV::FeatureVendorXqcisls,
+ RISCV::FeatureVendorXqcisync,
};
static constexpr FeatureBitset XSfVectorGroup = {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 0b08dfb31741d..db305b0083415 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -299,6 +299,7 @@ enum OperandType : unsigned {
OPERAND_UIMM5_PLUS1,
OPERAND_UIMM5_GE6_PLUS1,
OPERAND_UIMM5_LSB0,
+ OPERAND_UIMM5_SLIST,
OPERAND_UIMM6,
OPERAND_UIMM6_LSB0,
OPERAND_UIMM7,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index e10a2b1b3e476..72bdda7b26509 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -84,6 +84,10 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ uint64_t getImmOpValueSlist(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
uint64_t getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
@@ -404,6 +408,36 @@ RISCVMCCodeEmitter::getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,
return 0;
}
+uint64_t
+RISCVMCCodeEmitter::getImmOpValueSlist(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ assert(MO.isImm() && "Slist operand must be immediate");
+
+ uint64_t Res = MO.getImm();
+ switch (Res) {
+ case 0:
+ return 0;
+ case 1:
+ return 1;
+ case 2:
+ return 2;
+ case 4:
+ return 3;
+ case 8:
+ return 4;
+ case 16:
+ return 5;
+ case 15:
+ return 6;
+ case 31:
+ return 7;
+ default:
+ llvm_unreachable("Unhandled Slist value!");
+ }
+}
+
uint64_t
RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 761cfbea76734..e207b7fcd6219 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1438,6 +1438,14 @@ def HasVendorXqcisim
AssemblerPredicate<(all_of FeatureVendorXqcisim),
"'Xqcisim' (Qualcomm uC Simulation Hint Extension)">;
+def FeatureVendorXqcisync
+ : RISCVExperimentalExtension<0, 2, "Qualcomm uC Sync Delay Extension",
+ [FeatureStdExtZca]>;
+def HasVendorXqcisync
+ : Predicate<"Subtarget->hasVendorXqcisync()">,
+ AssemblerPredicate<(all_of FeatureVendorXqcisync),
+ "'Xqcisync' (Qualcomm uC Sync Delay Extension)">;
+
// Rivos Extension(s)
def FeatureVendorXRivosVisni
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index c009bd3b24682..196dd4765cc5f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -50,6 +50,21 @@ def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
let OperandType = "OPERAND_UIMM5_GE6_PLUS1";
}
+def uimm5slist : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
+ [{return ((Imm == 0) ||
+ (Imm == 1) ||
+ (Imm == 2) ||
+ (Imm == 4) ||
+ (Imm == 8) ||
+ (Imm == 16) ||
+ (Imm == 15) ||
+ (Imm == 31));}]> {
+ let ParserMatchClass = UImmAsmOperand<5, "Slist">;
+ let EncoderMethod = "getImmOpValueSlist";
+ let DecoderMethod = "decodeUImmSlistOperand";
+ let OperandType = "OPERAND_UIMM5_SLIST";
+}
+
def uimm10 : RISCVUImmLeafOp<10>;
def uimm11 : RISCVUImmLeafOp<11>;
@@ -364,6 +379,27 @@ class QCISim_RS1<bits<4> imm11_8, string opcodestr>
let imm12 = {imm11_8, 0b00000000};
}
+let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
+class QCISync_UIMM5<bits<4> imm11_8, string opcodestr>
+ : RVInstI<0b011, OPC_OP_IMM, (outs), (ins uimm5:$imm5), opcodestr, "$imm5">
+{
+ bits<5> imm5;
+
+ let rs1 = 0;
+ let rd = 0;
+ let imm12 = {imm11_8, 0b000, imm5};
+}
+
+let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
+class QCIRVInst16CBSYNC<bits<3> imm5_func2, string OpcodeStr>
+ : RVInst16CB<0b100, 0b01, (outs), (ins uimm5slist:$slist), OpcodeStr, "$slist"> {
+ bits<3> slist;
+
+ let Inst{6-2} = 0;
+ let Inst{9-7} = slist;
+ let Inst{12-10} = imm5_func2;
+}
+
class QCIRVInstEIBase<bits<3> funct3, bits<2> funct2, dag outs,
dag ins, string opcodestr, string argstr>
: RVInst48<outs, ins, opcodestr, argstr, [], InstFormatOther> {
@@ -744,6 +780,27 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVendorXqcilia, IsRV32]
+let Predicates = [HasVendorXqcisync, IsRV32] in {
+ def QC_SYNC : QCISync_UIMM5<0b0001, "qc.sync">;
+ def QC_SYNCR : QCISync_UIMM5<0b0010, "qc.syncr">;
+ def QC_SYNCWF : QCISync_UIMM5<0b0100, "qc.syncwf">;
+ def QC_SYNCWL : QCISync_UIMM5<0b1000, "qc.syncwl">;
+
+ def QC_C_SYNC : QCIRVInst16CBSYNC<0b000, "qc.c.sync">;
+ def QC_C_SYNCR : QCIRVInst16CBSYNC<0b001, "qc.c.syncr">;
+ def QC_C_SYNCWF : QCIRVInst16CBSYNC<0b100, "qc.c.syncwf">;
+ def QC_C_SYNCWL : QCIRVInst16CBSYNC<0b101, "qc.c.syncwl">;
+
+ let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
+ def QC_C_DELAY : RVInst16CI<0b000, 0b10, (outs),
+ (ins uimm5nonzero:$imm),
+ "qc.c.delay", "$imm"> {
+ let Inst{12} = 0;
+ let Inst{11-7} = 0;
+ let Inst{6-2} = imm{4-0};
+ }
+} // Predicates = [HasVendorXqcisync, IsRV32]
+
let Predicates = [HasVendorXqcisim, IsRV32] in {
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
def QC_PSYSCALLI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm10:$imm10),
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 4cb263b028625..cb161b0bfad5f 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -744,10 +744,10 @@ Error RISCVISAInfo::checkDependency() {
bool HasXqccmp = Exts.count("xqccmp") != 0;
static constexpr StringLiteral XqciExts[] = {
- {"xqcia"}, {"xqciac"}, {"xqcibi"}, {"xqcibm"},
- {"xqcicli"}, {"xqcicm"}, {"xqcics"}, {"xqcicsr"},
- {"xqciint"}, {"xqcilb"}, {"xqcili"}, {"xqcilia"},
- {"xqcilo"}, {"xqcilsm"}, {"xqcisim"}, {"xqcisls"}};
+ {"xqcia"}, {"xqciac"}, {"xqcibi"}, {"xqcibm"}, {"xqcicli"},
+ {"xqcicm"}, {"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilb"},
+ {"xqcili"}, {"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisim"},
+ {"xqcisls"}, {"xqcisync"}};
static constexpr StringLiteral ZcdOverlaps[] = {
{"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqciac"}, {"xqcicm"}};
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 82b2b25add735..9a4b94b4bb371 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -97,6 +97,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisim %s -o - | FileCheck --check-prefix=RV32XQCISIM %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisync %s -o - | FileCheck --check-prefix=RV32XQCISYNC %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
; RUN: llc -mtriple=riscv32 -mattr=+zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
@@ -425,6 +426,7 @@
; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"
; RV32XQCISIM: attribute 5, "rv32i2p1_zca1p0_xqcisim0p2"
+; RV32XQCISYNC: attribute 5, "rv32i2p1_zca1p0_xqcisync0p2"
; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"
; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc1p0"
diff --git a/llvm/test/MC/RISCV/xqcisync-invalid.s b/llvm/test/MC/RISCV/xqcisync-invalid.s
new file mode 100644
index 0000000000000..24b80eec1b1e8
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqcisync-invalid.s
@@ -0,0 +1,121 @@
+# Xqcisync - Qualcomm uC Sync Delay Extension
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcisync < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
+# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcisync < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
+
+# CHECK-PLUS: :[[@LINE+1]]:12: error: immediate must be an integer in the range [1, 31]
+qc.c.delay 34
+
+# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+qc.c.delay 11, 12
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.c.delay
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisync' (Qualcomm uC Sync Delay Extension)
+qc.c.delay 10
+
+
+# CHECK-PLUS: :[[@LINE+1]]:9: error: immediate must be an integer in the range [0, 31]
+qc.sync 45
+
+# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
+qc.sync 22, x4
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.sync
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisync' (Qualcomm uC Sync Delay Extension)
+qc.sync 8
+
+
+# CHECK-PLUS: :[[@LINE+1]]:10: error: immediate must be an integer in the range [0, 31]
+qc.syncr 56
+
+# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
+qc.syncr 31, 45
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.syncr
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisync' (Qualcomm uC Sync Delay Extension)
+qc.syncr 23
+
+
+# CHECK-PLUS: :[[@LINE+1]]:11: error: immediate must be an integer in the range [0, 31]
+qc.syncwf 88
+
+# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
+qc.syncwf 5, 44
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.syncwf
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisync' (Qualcomm uC Sync Delay Extension)
+qc.syncwf 31
+
+
+# CHECK-PLUS: :[[@LINE+1]]:11: error: immediate must be an integer in the range [0, 31]
+qc.syncwl 99
+
+# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction
+qc.syncwl 11, x10
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.syncwl
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisync' (Qualcomm uC Sync Delay Extension)
+qc.syncwl 1
+
+
+# CHECK-PLUS: :[[@LINE+1]]:11: error: immediate must be one of: 0, 1, 2, 4, 8, 15, 16, 31 in the range [0, 31]
+qc.c.sync 45
+
+# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction
+qc.c.sync 31, x4
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.c.sync
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisync' (Qualcomm uC Sync Delay Extension)
+qc.c.sync 8
+
+
+# CHECK-PLUS: :[[@LINE+1]]:12: error: immediate must be one of: 0, 1, 2, 4, 8, 15, 16, 31 in the range [0, 31]
+qc.c.syncr 56
+
+# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+qc.c.syncr 31, 45
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.c.syncr
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisync' (Qualcomm uC Sync Delay Extension)
+qc.c.syncr 8
+
+
+# CHECK-PLUS: :[[@LINE+1]]:13: error: immediate must be one of: 0, 1, 2, 4, 8, 15, 16, 31 in the range [0, 31]
+qc.c.syncwf 88
+
+# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+qc.c.syncwf 8, 44
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.c.syncwf
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisync' (Qualcomm uC Sync Delay Extension)
+qc.c.syncwf 31
+
+
+# CHECK-PLUS: :[[@LINE+1]]:13: error: immediate must be one of: 0, 1, 2, 4, 8, 15, 16, 31 in the range [0, 31]
+qc.c.syncwl 99
+
+# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
+qc.c.syncwl 15, x10
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.c.syncwl
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisync' (Qualcomm uC Sync Delay Extension)
+qc.c.syncwl 1
diff --git a/llvm/test/MC/RISCV/xqcisync-valid.s b/llvm/test/MC/RISCV/xqcisync-valid.s
new file mode 100644
index 0000000000000..3eedf99247b22
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqcisync-valid.s
@@ -0,0 +1,47 @@
+# Xqcisync - Qualcomm uC Sync Delay Extension
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisync -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcisync -M no-aliases --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisync -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcisync --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: qc.c.delay 10
+# CHECK-ENC: encoding: [0x2a,0x00]
+qc.c.delay 10
+
+# CHECK-INST: qc.syn...
[truncated]
|
topperc
reviewed
Mar 20, 2025
| case Match_InvalidUImm5Slist: | ||
| return generateImmOutOfRangeError( | ||
| Operands, ErrorInfo, 0, (1 << 5) - 1, | ||
| "immediate must be one of: 0, 1, 2, 4, 8, 15, 16, 31 in the range "); |
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Is the "in the range" useful here after listing all the values? Maybe we should just do
return Error(ErrorLoc, "immediate must be one of: 0, 1, 2, 4, 8, 15, 16, 31");
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Changed. Took ErrorLoc from other similar error messages in the file. This new error message makes more sense.
Change-Id: I4d10a0480e008419f6e962e7467b9076f7bd9826
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I've already subscribed to pr-subscribers-backend:RISC-V but the change renaming VariantKind to Specifier was directly commited to the repo. Is there a way I can get notified for direct commits as well? |
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@svs-quic I've reverted this PR for now. I'm happy to try your revised patch. Thanks! |
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…nsion (#132184)" This reverts commit 3840f78. Multiple builtbot failures have been reported: llvm/llvm-project#132184
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hi @kazutakahirata i had fixed the failure in #132502 and was just about to merge it. |
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Oops. Sorry about that. Would you mind relanding this and #132502, maybe in a single merge? |
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…on (llvm#132184)"" This reverts commit fe7776e.
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…32184)" (#132520) With a minor fix for the build failures. Original message: This extension adds nine instructions, eight for non-memory-mapped devices synchronization and delay instruction. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli [email protected]
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This extension adds nine instructions, eight for non-memory-mapped devices synchronization and delay instruction.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0
This patch adds assembler only support.
Co-authored-by: Sudharsan Veeravalli [email protected]