Skip to content
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
16 changes: 9 additions & 7 deletions mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -136,9 +136,13 @@ struct GPUShuffleOpLowering : public ConvertOpToLLVMPattern<gpu::ShuffleOp> {
matchAndRewrite(gpu::ShuffleOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
Location loc = op->getLoc();
Value initShflValue = adaptor.getValue();
Type shflType = initShflValue.getType();
// TODO: Add support for non 32-bit shuffle values.
if (adaptor.getValue().getType().getIntOrFloatBitWidth() != 32)
return failure();
if (!shflType.isIntOrFloat() || shflType.getIntOrFloatBitWidth() != 32)
return rewriter.notifyMatchFailure(
op, "only 32-bit int/float types are supported");

const unsigned indexBitwidth = getTypeConverter()->getIndexTypeBitwidth();
Value srcLaneId = getLaneId(rewriter, loc, indexBitwidth);

Expand Down Expand Up @@ -175,16 +179,14 @@ struct GPUShuffleOpLowering : public ConvertOpToLLVMPattern<gpu::ShuffleOp> {
Value two = rewriter.create<LLVM::ConstantOp>(loc, int32Type, 2);
Value dwordAlignedDstLane =
rewriter.create<LLVM::ShlOp>(loc, int32Type, selectDstLane, two);
Value initShflValue = adaptor.getValue();
if (adaptor.getValue().getType().isF32()) {
if (shflType.isF32()) {
initShflValue =
rewriter.create<LLVM::BitcastOp>(loc, int32Type, initShflValue);
}
Value shflValue = rewriter.create<ROCDL::DsBpermuteOp>(
loc, int32Type, dwordAlignedDstLane, initShflValue);
if (adaptor.getValue().getType().isF32()) {
shflValue = rewriter.create<LLVM::BitcastOp>(
loc, adaptor.getValue().getType(), shflValue);
if (shflType.isF32()) {
shflValue = rewriter.create<LLVM::BitcastOp>(loc, shflType, shflValue);
}
rewriter.replaceOp(op, {shflValue, isActiveSrcLane});
return success();
Expand Down
5 changes: 3 additions & 2 deletions mlir/lib/Dialect/GPU/Transforms/ShuffleRewriter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -40,8 +40,9 @@ struct GpuShuffleRewriter : public OpRewritePattern<gpu::ShuffleOp> {
auto i64 = rewriter.getI64Type();

// If the type of the value is either i32 or f32, the op is already valid.
if (valueType.getIntOrFloatBitWidth() == 32)
return failure();
if (!valueType.isIntOrFloat() || valueType.getIntOrFloatBitWidth() != 64)
return rewriter.notifyMatchFailure(
op, "only 64-bit int/float types are supported");

Value lo, hi;

Expand Down
13 changes: 13 additions & 0 deletions mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-unsupported.mlir
Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
// RUN: mlir-opt %s -convert-gpu-to-rocdl -verify-diagnostics

gpu.module @test_module {
// ROCDL lowering only suport shuffles for 32bit ints/floats, but they
// shouldn't crash on unsupported types.
func.func @gpu_shuffle_unsupported(%arg0 : vector<4xf16>) -> vector<4xf16> {
%offset = arith.constant 4 : i32
%width = arith.constant 64 : i32
// expected-error @+1 {{failed to legalize operation 'gpu.shuffle'}}
%shfl, %pred = gpu.shuffle xor %arg0, %offset, %width : vector<4xf16>
return %shfl : vector<4xf16>
}
}
11 changes: 11 additions & 0 deletions mlir/test/Dialect/GPU/shuffle-rewrite.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -49,3 +49,14 @@ module {
return
}
}

// -----

// CHECK-LABEL: @gpu_shuffle_unsupported
func.func @gpu_shuffle_unsupported(%arg0 : vector<4xf16>) -> vector<4xf16> {
%offset = arith.constant 4 : i32
%width = arith.constant 64 : i32
// CHECK: gpu.shuffle xor %{{.*}}, %{{.*}}, %{{.*}} : vector<4xf16>
%shfl, %pred = gpu.shuffle xor %arg0, %offset, %width : vector<4xf16>
return %shfl : vector<4xf16>
}