[DAGCombiner] Fold and/or of NaN SETCC #135645
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Member
|
@llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-llvm-selectiondag Author: Alex MacLean (AlexMaclean) ChangesFold an AND or OR of two NaN SETCC nodes into a single SETCC where possible. This optimization already exists in InstCombine but adding in here as well can allow for additional folding if more logical operations are exposed. Full diff: https://github.com/llvm/llvm-project/pull/135645.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8136f1794775e..8eb3f95a30989 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6427,6 +6427,12 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
}
}
+ if (LHS0 == LHS1 && RHS0 == RHS1 && CCL == CCR &&
+ LHS0.getValueType() == RHS0.getValueType() &&
+ ((LogicOp->getOpcode() == ISD::AND && CCL == ISD::SETO) ||
+ (LogicOp->getOpcode() == ISD::OR && CCL == ISD::SETUO)))
+ return DAG.getSetCC(DL, VT, LHS0, RHS0, CCL);
+
if (TargetPreference == AndOrSETCCFoldKind::None)
return SDValue();
diff --git a/llvm/test/CodeGen/NVPTX/and-or-setcc.ll b/llvm/test/CodeGen/NVPTX/and-or-setcc.ll
new file mode 100644
index 0000000000000..21be9df94d553
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/and-or-setcc.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=nvptx64 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 | %ptxas-verify %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i1 @and_ord(float %a, float %b) {
+; CHECK-LABEL: and_ord(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .f32 %f<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.f32 %f1, [and_ord_param_0];
+; CHECK-NEXT: ld.param.f32 %f2, [and_ord_param_1];
+; CHECK-NEXT: setp.num.f32 %p1, %f1, %f2;
+; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+ %c = fcmp ord float %a, 0.0
+ %d = fcmp ord float %b, 0.0
+ %e = and i1 %c, %d
+ ret i1 %e
+}
+
+define i1 @or_uno(float %a, float %b) {
+; CHECK-LABEL: or_uno(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .f32 %f<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.f32 %f1, [or_uno_param_0];
+; CHECK-NEXT: ld.param.f32 %f2, [or_uno_param_1];
+; CHECK-NEXT: setp.nan.f32 %p1, %f1, %f2;
+; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+ %c = fcmp uno float %a, 0.0
+ %d = fcmp uno float %b, 0.0
+ %e = or i1 %c, %d
+ ret i1 %e
+}
|
Member
|
@llvm/pr-subscribers-backend-nvptx Author: Alex MacLean (AlexMaclean) ChangesFold an AND or OR of two NaN SETCC nodes into a single SETCC where possible. This optimization already exists in InstCombine but adding in here as well can allow for additional folding if more logical operations are exposed. Full diff: https://github.com/llvm/llvm-project/pull/135645.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8136f1794775e..8eb3f95a30989 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6427,6 +6427,12 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
}
}
+ if (LHS0 == LHS1 && RHS0 == RHS1 && CCL == CCR &&
+ LHS0.getValueType() == RHS0.getValueType() &&
+ ((LogicOp->getOpcode() == ISD::AND && CCL == ISD::SETO) ||
+ (LogicOp->getOpcode() == ISD::OR && CCL == ISD::SETUO)))
+ return DAG.getSetCC(DL, VT, LHS0, RHS0, CCL);
+
if (TargetPreference == AndOrSETCCFoldKind::None)
return SDValue();
diff --git a/llvm/test/CodeGen/NVPTX/and-or-setcc.ll b/llvm/test/CodeGen/NVPTX/and-or-setcc.ll
new file mode 100644
index 0000000000000..21be9df94d553
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/and-or-setcc.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=nvptx64 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 | %ptxas-verify %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i1 @and_ord(float %a, float %b) {
+; CHECK-LABEL: and_ord(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .f32 %f<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.f32 %f1, [and_ord_param_0];
+; CHECK-NEXT: ld.param.f32 %f2, [and_ord_param_1];
+; CHECK-NEXT: setp.num.f32 %p1, %f1, %f2;
+; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+ %c = fcmp ord float %a, 0.0
+ %d = fcmp ord float %b, 0.0
+ %e = and i1 %c, %d
+ ret i1 %e
+}
+
+define i1 @or_uno(float %a, float %b) {
+; CHECK-LABEL: or_uno(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .f32 %f<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.f32 %f1, [or_uno_param_0];
+; CHECK-NEXT: ld.param.f32 %f2, [or_uno_param_1];
+; CHECK-NEXT: setp.nan.f32 %p1, %f1, %f2;
+; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+ %c = fcmp uno float %a, 0.0
+ %d = fcmp uno float %b, 0.0
+ %e = or i1 %c, %d
+ ret i1 %e
+}
|
Artem-B
reviewed
Apr 14, 2025
AlexMaclean
force-pushed
the
dev/amaclean/upstream/and-or-fcmp
branch
from
84c760a to
238ca4b
Compare
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/10/builds/3573 Here is the relevant piece of the build log for the reference |
arsenm
reviewed
Apr 17, 2025
| %d = fcmp uno float %b, 0.0 | ||
| %e = or i1 %c, %d | ||
| ret i1 %e | ||
| } |
Contributor
There was a problem hiding this comment.
Should also do vector tests
Member
Author
There was a problem hiding this comment.
Apologies, looks like I committed this change prematurely. I've addressed this comment in a follow up here #136168. Please take a look when you have a minute.
| ; RUN: llc < %s -mtriple=nvptx64 | FileCheck %s | ||
| ; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 | %ptxas-verify %} | ||
|
|
||
| target triple = "nvptx64-nvidia-cuda" |
AlexMaclean
added a commit
that referenced
this pull request
Apr 18, 2025
Follow up to #135645 to address test cleanup review.
IanWood1
pushed a commit
to IanWood1/llvm-project
that referenced
this pull request
May 6, 2025
Follow up to llvm#135645 to address test cleanup review.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
5 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Fold an AND or OR of two NaN SETCC nodes into a single SETCC where possible. This optimization already exists in InstCombine but adding in here as well can allow for additional folding if more logical operations are exposed.