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Reapply "[AMDGPU][GlobalISel] Properly handle lane op lowering for larger vector types (#132358)" #135758

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Merged
merged 1 commit into from
Apr 16, 2025
Merged

Reapply "[AMDGPU][GlobalISel] Properly handle lane op lowering for larger vector types (#132358)" #135758

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12 changes: 10 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5580,6 +5580,7 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
return false;

LLT PartialResTy = LLT::scalar(SplitSize);
bool NeedsBitcast = false;
if (Ty.isVector()) {
LLT EltTy = Ty.getElementType();
unsigned EltSize = EltTy.getSizeInBits();
Expand All @@ -5588,8 +5589,10 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
} else if (EltSize == 16 || EltSize == 32) {
unsigned NElem = SplitSize / EltSize;
PartialResTy = Ty.changeElementCount(ElementCount::getFixed(NElem));
} else {
// Handle all other cases via S32/S64 pieces
NeedsBitcast = true;
}
// Handle all other cases via S32/S64 pieces;
}

SmallVector<Register, 4> PartialRes;
Expand All @@ -5615,7 +5618,12 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
PartialRes.push_back(createLaneOp(Src0, Src1, Src2, PartialResTy));
}

B.buildMergeLikeInstr(DstReg, PartialRes);
if (NeedsBitcast)
B.buildBitcast(DstReg, B.buildMergeLikeInstr(
LLT::scalar(Ty.getSizeInBits()), PartialRes));
else
B.buildMergeLikeInstr(DstReg, PartialRes);

MI.eraseFromParent();
return true;
}
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