[RISCV] Add Andes N45/NX45 processor definition #136670
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Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU architecture with rv[32|64]imafdc_zba_zbb_zbs march. The overviews for N45/NX45: https://www.andestech.com/en/products-solutions/andescore-processors/riscv-n45/ https://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx45/ Scheduling model will be implemented in a later PR.
tclin914
requested review from
asi-sc,
kito-cheng,
lenary,
mshockwave and
wangpc-pp
llvmbot
added
clang
Member
|
@llvm/pr-subscribers-clang-driver @llvm/pr-subscribers-clang Author: Jim Lin (tclin914) ChangesAndes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU architecture implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for N45/NX45: Scheduling model will be implemented in a later PR. Full diff: https://github.com/llvm/llvm-project/pull/136670.diff 4 Files Affected:
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index c2314efd34aa6..19da8ede26a40 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -692,3 +692,37 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s
+// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-N45-SAME: "-target-abi" "ilp32d"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-n45 | FileCheck -check-prefix=MTUNE-ANDES-N45 %s
+// MTUNE-ANDES-N45: "-tune-cpu" "andes-n45"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-nx45 | FileCheck -check-prefix=MCPU-ANDES-NX45 %s
+// MCPU-ANDES-NX45: "-target-cpu" "andes-nx45"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-NX45-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-nx45 | FileCheck -check-prefix=MTUNE-ANDES-NX45 %s
+// MTUNE-ANDES-NX45: "-tune-cpu" "andes-nx45"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 199916f70c14f..cd8a8bf95dd7a 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -5,7 +5,8 @@
// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
// RISCV32: error: unknown target CPU 'not-a-cpu'
// RISCV32-NEXT: note: valid target CPU values are:
-// RISCV32-SAME: {{^}} generic-rv32
+// RISCV32-SAME: {{^}} andes-n45
+// RISCV32-SAME: {{^}}, generic-rv32
// RISCV32-SAME: {{^}}, rocket-rv32
// RISCV32-SAME: {{^}}, rp2350-hazard3
// RISCV32-SAME: {{^}}, sifive-e20
@@ -24,7 +25,8 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
// RISCV64-NEXT: note: valid target CPU values are:
-// RISCV64-SAME: {{^}} generic-rv64
+// RISCV64-SAME: {{^}} andes-nx45
+// RISCV64-SAME: {{^}}, generic-rv64
// RISCV64-SAME: {{^}}, mips-p8700
// RISCV64-SAME: {{^}}, rocket-rv64
// RISCV64-SAME: {{^}}, sifive-p450
@@ -52,7 +54,8 @@
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV32-NEXT: note: valid target CPU values are:
-// TUNE-RISCV32-SAME: {{^}} generic-rv32
+// TUNE-RISCV32-SAME: {{^}} andes-n45
+// TUNE-RISCV32-SAME: {{^}}, generic-rv32
// TUNE-RISCV32-SAME: {{^}}, rocket-rv32
// TUNE-RISCV32-SAME: {{^}}, rp2350-hazard3
// TUNE-RISCV32-SAME: {{^}}, sifive-e20
@@ -75,7 +78,8 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV64-NEXT: note: valid target CPU values are:
-// TUNE-RISCV64-SAME: {{^}} generic-rv64
+// TUNE-RISCV64-SAME: {{^}} andes-nx45
+// TUNE-RISCV64-SAME: {{^}}, generic-rv64
// TUNE-RISCV64-SAME: {{^}}, mips-p8700
// TUNE-RISCV64-SAME: {{^}}, rocket-rv64
// TUNE-RISCV64-SAME: {{^}}, sifive-p450
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index cc4fd38944ff6..a3f91224ca24e 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -168,6 +168,7 @@ Changes to the RISC-V Backend
and branch and linker relaxation. This can be disabled with ``.option noexact``,
which is also the default.
* `-mcpu=xiangshan-kunminghu` was added.
+* `-mcpu=andes-n45` and `-mcpu=andes-nx45` were added.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 4b288a9cfcb49..abc7889b3a0e6 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -625,3 +625,33 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
FeatureStdExtZbkb,
FeatureStdExtZcb,
FeatureStdExtZcmp]>;
+
+def ANDES_N45 : RISCVProcessorModel<"andes-n45",
+ NoSchedModel,
+ [Feature32Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs]>;
+
+def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs]>;
|
Member
|
@llvm/pr-subscribers-backend-risc-v Author: Jim Lin (tclin914) ChangesAndes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU architecture implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for N45/NX45: Scheduling model will be implemented in a later PR. Full diff: https://github.com/llvm/llvm-project/pull/136670.diff 4 Files Affected:
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index c2314efd34aa6..19da8ede26a40 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -692,3 +692,37 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s
+// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-N45-SAME: "-target-abi" "ilp32d"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-n45 | FileCheck -check-prefix=MTUNE-ANDES-N45 %s
+// MTUNE-ANDES-N45: "-tune-cpu" "andes-n45"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-nx45 | FileCheck -check-prefix=MCPU-ANDES-NX45 %s
+// MCPU-ANDES-NX45: "-target-cpu" "andes-nx45"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-NX45-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-nx45 | FileCheck -check-prefix=MTUNE-ANDES-NX45 %s
+// MTUNE-ANDES-NX45: "-tune-cpu" "andes-nx45"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 199916f70c14f..cd8a8bf95dd7a 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -5,7 +5,8 @@
// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
// RISCV32: error: unknown target CPU 'not-a-cpu'
// RISCV32-NEXT: note: valid target CPU values are:
-// RISCV32-SAME: {{^}} generic-rv32
+// RISCV32-SAME: {{^}} andes-n45
+// RISCV32-SAME: {{^}}, generic-rv32
// RISCV32-SAME: {{^}}, rocket-rv32
// RISCV32-SAME: {{^}}, rp2350-hazard3
// RISCV32-SAME: {{^}}, sifive-e20
@@ -24,7 +25,8 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
// RISCV64-NEXT: note: valid target CPU values are:
-// RISCV64-SAME: {{^}} generic-rv64
+// RISCV64-SAME: {{^}} andes-nx45
+// RISCV64-SAME: {{^}}, generic-rv64
// RISCV64-SAME: {{^}}, mips-p8700
// RISCV64-SAME: {{^}}, rocket-rv64
// RISCV64-SAME: {{^}}, sifive-p450
@@ -52,7 +54,8 @@
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV32-NEXT: note: valid target CPU values are:
-// TUNE-RISCV32-SAME: {{^}} generic-rv32
+// TUNE-RISCV32-SAME: {{^}} andes-n45
+// TUNE-RISCV32-SAME: {{^}}, generic-rv32
// TUNE-RISCV32-SAME: {{^}}, rocket-rv32
// TUNE-RISCV32-SAME: {{^}}, rp2350-hazard3
// TUNE-RISCV32-SAME: {{^}}, sifive-e20
@@ -75,7 +78,8 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV64-NEXT: note: valid target CPU values are:
-// TUNE-RISCV64-SAME: {{^}} generic-rv64
+// TUNE-RISCV64-SAME: {{^}} andes-nx45
+// TUNE-RISCV64-SAME: {{^}}, generic-rv64
// TUNE-RISCV64-SAME: {{^}}, mips-p8700
// TUNE-RISCV64-SAME: {{^}}, rocket-rv64
// TUNE-RISCV64-SAME: {{^}}, sifive-p450
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index cc4fd38944ff6..a3f91224ca24e 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -168,6 +168,7 @@ Changes to the RISC-V Backend
and branch and linker relaxation. This can be disabled with ``.option noexact``,
which is also the default.
* `-mcpu=xiangshan-kunminghu` was added.
+* `-mcpu=andes-n45` and `-mcpu=andes-nx45` were added.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 4b288a9cfcb49..abc7889b3a0e6 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -625,3 +625,33 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
FeatureStdExtZbkb,
FeatureStdExtZcb,
FeatureStdExtZcmp]>;
+
+def ANDES_N45 : RISCVProcessorModel<"andes-n45",
+ NoSchedModel,
+ [Feature32Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs]>;
+
+def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs]>;
|
mshockwave
reviewed
Apr 22, 2025
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/59/builds/16478 Here is the relevant piece of the build log for the reference |
IanWood1
pushed a commit
to IanWood1/llvm-project
that referenced
this pull request
May 6, 2025
Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU architecture implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for N45/NX45: https://www.andestech.com/en/products-solutions/andescore-processors/riscv-n45/ https://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx45/ Scheduling model will be implemented in a later PR.
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Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU architecture implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider.
The overviews for N45/NX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-n45/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx45/
Scheduling model will be implemented in a later PR.