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[RISCV] Add Andes N45/NX45 processor definition #136670

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Merged
merged 2 commits into from
Apr 23, 2025
Merged

[RISCV] Add Andes N45/NX45 processor definition #136670

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df3a0b2
[RISCV] Add Andes N45/NX45 processor definition
tclin914 Apr 22, 2025
0dadc5f
Use FeatureStdExtB instead
tclin914 Apr 23, 2025
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34 changes: 34 additions & 0 deletions clang/test/Driver/riscv-cpus.c
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Expand Up @@ -692,3 +692,37 @@

// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"

// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s
// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
// MCPU-ANDES-N45-SAME: "-target-feature" "+m"
// MCPU-ANDES-N45-SAME: "-target-feature" "+a"
// MCPU-ANDES-N45-SAME: "-target-feature" "+f"
// MCPU-ANDES-N45-SAME: "-target-feature" "+d"
// MCPU-ANDES-N45-SAME: "-target-feature" "+c"
// MCPU-ANDES-N45-SAME: "-target-feature" "+zicsr"
// MCPU-ANDES-N45-SAME: "-target-feature" "+zifencei"
// MCPU-ANDES-N45-SAME: "-target-feature" "+zba"
// MCPU-ANDES-N45-SAME: "-target-feature" "+zbb"
// MCPU-ANDES-N45-SAME: "-target-feature" "+zbs"
// MCPU-ANDES-N45-SAME: "-target-abi" "ilp32d"

// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-n45 | FileCheck -check-prefix=MTUNE-ANDES-N45 %s
// MTUNE-ANDES-N45: "-tune-cpu" "andes-n45"

// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-nx45 | FileCheck -check-prefix=MCPU-ANDES-NX45 %s
// MCPU-ANDES-NX45: "-target-cpu" "andes-nx45"
// MCPU-ANDES-NX45-SAME: "-target-feature" "+m"
// MCPU-ANDES-NX45-SAME: "-target-feature" "+a"
// MCPU-ANDES-NX45-SAME: "-target-feature" "+f"
// MCPU-ANDES-NX45-SAME: "-target-feature" "+d"
// MCPU-ANDES-NX45-SAME: "-target-feature" "+c"
// MCPU-ANDES-NX45-SAME: "-target-feature" "+zicsr"
// MCPU-ANDES-NX45-SAME: "-target-feature" "+zifencei"
// MCPU-ANDES-NX45-SAME: "-target-feature" "+zba"
// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbb"
// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbs"
// MCPU-ANDES-NX45-SAME: "-target-abi" "lp64d"

// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-nx45 | FileCheck -check-prefix=MTUNE-ANDES-NX45 %s
// MTUNE-ANDES-NX45: "-tune-cpu" "andes-nx45"
12 changes: 8 additions & 4 deletions clang/test/Misc/target-invalid-cpu-note/riscv.c
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Expand Up @@ -5,7 +5,8 @@
// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
// RISCV32: error: unknown target CPU 'not-a-cpu'
// RISCV32-NEXT: note: valid target CPU values are:
// RISCV32-SAME: {{^}} generic-rv32
// RISCV32-SAME: {{^}} andes-n45
// RISCV32-SAME: {{^}}, generic-rv32
// RISCV32-SAME: {{^}}, rocket-rv32
// RISCV32-SAME: {{^}}, rp2350-hazard3
// RISCV32-SAME: {{^}}, sifive-e20
Expand All @@ -24,7 +25,8 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
// RISCV64-NEXT: note: valid target CPU values are:
// RISCV64-SAME: {{^}} generic-rv64
// RISCV64-SAME: {{^}} andes-nx45
// RISCV64-SAME: {{^}}, generic-rv64
// RISCV64-SAME: {{^}}, mips-p8700
// RISCV64-SAME: {{^}}, rocket-rv64
// RISCV64-SAME: {{^}}, sifive-p450
Expand Down Expand Up @@ -52,7 +54,8 @@
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV32-NEXT: note: valid target CPU values are:
// TUNE-RISCV32-SAME: {{^}} generic-rv32
// TUNE-RISCV32-SAME: {{^}} andes-n45
// TUNE-RISCV32-SAME: {{^}}, generic-rv32
// TUNE-RISCV32-SAME: {{^}}, rocket-rv32
// TUNE-RISCV32-SAME: {{^}}, rp2350-hazard3
// TUNE-RISCV32-SAME: {{^}}, sifive-e20
Expand All @@ -75,7 +78,8 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV64-NEXT: note: valid target CPU values are:
// TUNE-RISCV64-SAME: {{^}} generic-rv64
// TUNE-RISCV64-SAME: {{^}} andes-nx45
// TUNE-RISCV64-SAME: {{^}}, generic-rv64
// TUNE-RISCV64-SAME: {{^}}, mips-p8700
// TUNE-RISCV64-SAME: {{^}}, rocket-rv64
// TUNE-RISCV64-SAME: {{^}}, sifive-p450
Expand Down
1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -168,6 +168,7 @@ Changes to the RISC-V Backend
and branch and linker relaxation. This can be disabled with ``.option noexact``,
which is also the default.
* `-mcpu=xiangshan-kunminghu` was added.
* `-mcpu=andes-n45` and `-mcpu=andes-nx45` were added.

Changes to the WebAssembly Backend
----------------------------------
Expand Down
26 changes: 26 additions & 0 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Expand Up @@ -625,3 +625,29 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
FeatureStdExtZbkb,
FeatureStdExtZcb,
FeatureStdExtZcmp]>;

def ANDES_N45 : RISCVProcessorModel<"andes-n45",
NoSchedModel,
[Feature32Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
FeatureStdExtZifencei,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB]>;

def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
NoSchedModel,
[Feature64Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
FeatureStdExtZifencei,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB]>;
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