[RISCV] Add zihintpause LLVM/Clang intrinsic
#139519
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@llvm/pr-subscribers-llvm-ir @llvm/pr-subscribers-clang-codegen Author: Kiva (imkiva) ChangesThis PR adds the missing intrinsic Spec: https://five-embeddev.com/riscv-user-isa-manual/Priv-v1.12/zihintpause.html Full diff: https://github.com/llvm/llvm-project/pull/139519.diff 7 Files Affected:
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td
index 3263603a8a1cf..598ec2abeeae1 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -147,6 +147,13 @@ def ntl_load : RISCVBuiltin<"void(...)">;
def ntl_store : RISCVBuiltin<"void(...)">;
} // Features = "zihintntl", Attributes = [CustomTypeChecking]
+//===----------------------------------------------------------------------===//
+// Zihintpause extension.
+//===----------------------------------------------------------------------===//
+let Features = "zihintpause" in {
+def pause : RISCVBuiltin<"void(...)">;
+} // Features = "zihintntl"
+
//===----------------------------------------------------------------------===//
// XCV extensions.
//===----------------------------------------------------------------------===//
diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
index 3335239b0b6c2..0cd4f3c935e92 100644
--- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
@@ -357,6 +357,12 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
return Store;
}
+ // Zihintpause
+ case RISCV::BI__builtin_riscv_pause: {
+ llvm::Function *Fn = CGM.getIntrinsic(llvm::Intrinsic::riscv_pause);
+ return Builder.CreateCall(Fn, {});
+ }
+
// XCValu
case RISCV::BI__builtin_riscv_cv_alu_addN:
ID = Intrinsic::riscv_cv_alu_addN;
diff --git a/clang/test/CodeGen/RISCV/riscv-zihintpause.c b/clang/test/CodeGen/RISCV/riscv-zihintpause.c
new file mode 100644
index 0000000000000..76d2f289a075b
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-zihintpause.c
@@ -0,0 +1,14 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+#include <stdint.h>
+
+// CHECK-LABEL: @test_builtin_pause(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.riscv.pause()
+// CHECK-NEXT: ret void
+//
+void test_builtin_pause() {
+ __builtin_riscv_pause();
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 18b2883eb00e7..782c583db89de 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -1886,6 +1886,12 @@ let TargetPrefix = "riscv" in {
def int_riscv_vsm3me : RISCVBinaryAAXUnMasked;
} // TargetPrefix = "riscv"
+// Zihintpause extensions
+//===----------------------------------------------------------------------===//
+let TargetPrefix = "riscv" in {
+ def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+} // TargetPrefix = "riscv"
+
// Vendor extensions
//===----------------------------------------------------------------------===//
include "llvm/IR/IntrinsicsRISCVXTHead.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index e9bdeb88e4ca8..8a5b52e591433 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2242,6 +2242,9 @@ include "RISCVInstrInfoZclsd.td"
// Short Forward Branch
include "RISCVInstrInfoSFB.td"
+// Zihintpause extensions
+include "RISCVInstrInfoZihintpause.td"
+
//===----------------------------------------------------------------------===//
// Vendor extensions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td
new file mode 100644
index 0000000000000..60bfdf96c3f98
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td
@@ -0,0 +1,10 @@
+//===-- RISCVInstrInfoZihintpause.td -----------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+
+let Predicates = [HasStdExtZihintpause] in {
+ def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>;
+}
diff --git a/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
new file mode 100644
index 0000000000000..6c6f5e20a8b48
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+zihintpause -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RVPAUSE
+
+declare void @llvm.riscv.pause()
+
+define void @test_pause() {
+; RVPAUSE-LABEL: test_pause:
+; RVPAUSE: # %bb.0:
+; RVPAUSE-NEXT: pause
+; RVPAUSE-NEXT: ret
+ call void @llvm.riscv.pause()
+ ret void
+}
|
Member
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@llvm/pr-subscribers-backend-risc-v Author: Kiva (imkiva) ChangesThis PR adds the missing intrinsic Spec: https://five-embeddev.com/riscv-user-isa-manual/Priv-v1.12/zihintpause.html Full diff: https://github.com/llvm/llvm-project/pull/139519.diff 7 Files Affected:
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td
index 3263603a8a1cf..598ec2abeeae1 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -147,6 +147,13 @@ def ntl_load : RISCVBuiltin<"void(...)">;
def ntl_store : RISCVBuiltin<"void(...)">;
} // Features = "zihintntl", Attributes = [CustomTypeChecking]
+//===----------------------------------------------------------------------===//
+// Zihintpause extension.
+//===----------------------------------------------------------------------===//
+let Features = "zihintpause" in {
+def pause : RISCVBuiltin<"void(...)">;
+} // Features = "zihintntl"
+
//===----------------------------------------------------------------------===//
// XCV extensions.
//===----------------------------------------------------------------------===//
diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
index 3335239b0b6c2..0cd4f3c935e92 100644
--- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
@@ -357,6 +357,12 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
return Store;
}
+ // Zihintpause
+ case RISCV::BI__builtin_riscv_pause: {
+ llvm::Function *Fn = CGM.getIntrinsic(llvm::Intrinsic::riscv_pause);
+ return Builder.CreateCall(Fn, {});
+ }
+
// XCValu
case RISCV::BI__builtin_riscv_cv_alu_addN:
ID = Intrinsic::riscv_cv_alu_addN;
diff --git a/clang/test/CodeGen/RISCV/riscv-zihintpause.c b/clang/test/CodeGen/RISCV/riscv-zihintpause.c
new file mode 100644
index 0000000000000..76d2f289a075b
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-zihintpause.c
@@ -0,0 +1,14 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+#include <stdint.h>
+
+// CHECK-LABEL: @test_builtin_pause(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.riscv.pause()
+// CHECK-NEXT: ret void
+//
+void test_builtin_pause() {
+ __builtin_riscv_pause();
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 18b2883eb00e7..782c583db89de 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -1886,6 +1886,12 @@ let TargetPrefix = "riscv" in {
def int_riscv_vsm3me : RISCVBinaryAAXUnMasked;
} // TargetPrefix = "riscv"
+// Zihintpause extensions
+//===----------------------------------------------------------------------===//
+let TargetPrefix = "riscv" in {
+ def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+} // TargetPrefix = "riscv"
+
// Vendor extensions
//===----------------------------------------------------------------------===//
include "llvm/IR/IntrinsicsRISCVXTHead.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index e9bdeb88e4ca8..8a5b52e591433 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2242,6 +2242,9 @@ include "RISCVInstrInfoZclsd.td"
// Short Forward Branch
include "RISCVInstrInfoSFB.td"
+// Zihintpause extensions
+include "RISCVInstrInfoZihintpause.td"
+
//===----------------------------------------------------------------------===//
// Vendor extensions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td
new file mode 100644
index 0000000000000..60bfdf96c3f98
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td
@@ -0,0 +1,10 @@
+//===-- RISCVInstrInfoZihintpause.td -----------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+
+let Predicates = [HasStdExtZihintpause] in {
+ def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>;
+}
diff --git a/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
new file mode 100644
index 0000000000000..6c6f5e20a8b48
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+zihintpause -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RVPAUSE
+
+declare void @llvm.riscv.pause()
+
+define void @test_pause() {
+; RVPAUSE-LABEL: test_pause:
+; RVPAUSE: # %bb.0:
+; RVPAUSE-NEXT: pause
+; RVPAUSE-NEXT: ret
+ call void @llvm.riscv.pause()
+ ret void
+}
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el-ev
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wangpc-pp
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wangpc-pp
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wangpc-pp
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Do we need a header for it (just like others in https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#intrinsic-functions)?
topperc
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May 12, 2025
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Add to the RISC-V section of the clang release notes? |
lenary
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May 13, 2025
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We probably do, but for the moment this PR is just looking for |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/199/builds/3428 Here is the relevant piece of the build log for the reference |
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This PR adds the missing intrinsic
__builtin_riscv_pausefor the zihintpause extension.Spec: https://five-embeddev.com/riscv-user-isa-manual/Priv-v1.12/zihintpause.html
Fixes #129961