[RISCV] Add zihintpause LLVM/Clang intrinsic

clang/docs/ReleaseNotes.rst

@@ -790,6 +790,8 @@ RISC-V Support
 
 - `Zicsr` / `Zifencei` are allowed to be duplicated in the presence of `g` in `-march`.
 
+- Add support for the `__builtin_riscv_pause()` intrinsic from the `Zihintpause` extension.
+
 CUDA/HIP Language Changes
 ^^^^^^^^^^^^^^^^^^^^^^^^^
 

clang/include/clang/Basic/BuiltinsRISCV.td

@@ -147,6 +147,12 @@ def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
 
+//===----------------------------------------------------------------------===//
+// Zihintpause extension.
+//===----------------------------------------------------------------------===//
+let Features = "zihintpause", Attributes = [NoThrow] in
+def pause : RISCVBuiltin<"void()">;
+
 //===----------------------------------------------------------------------===//
 // XCV extensions.
 //===----------------------------------------------------------------------===//

clang/lib/CodeGen/TargetBuiltins/RISCV.cpp

@@ -357,6 +357,12 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
 
     return Store;
   }
+  // Zihintpause
+  case RISCV::BI__builtin_riscv_pause: {
+    llvm::Function *Fn = CGM.getIntrinsic(llvm::Intrinsic::riscv_pause);
+    return Builder.CreateCall(Fn, {});
+  }
+
   // XCValu
   case RISCV::BI__builtin_riscv_cv_alu_addN:
     ID = Intrinsic::riscv_cv_alu_addN;

clang/test/CodeGen/RISCV/riscv-zihintpause.c

@@ -0,0 +1,14 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \
+// RUN:     | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zihintpause -emit-llvm %s -o - \
+// RUN:     | FileCheck %s
+
+// CHECK-LABEL: @test_builtin_pause(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.riscv.pause()
+// CHECK-NEXT:    ret void
+//
+void test_builtin_pause() {
+    __builtin_riscv_pause();
+}

llvm/include/llvm/IR/IntrinsicsRISCV.td

@@ -1886,6 +1886,11 @@ let TargetPrefix = "riscv" in {
   def int_riscv_vsm3me   : RISCVBinaryAAXUnMasked;
 } // TargetPrefix = "riscv"
 
+// Zihintpause extensions
+//===----------------------------------------------------------------------===//
+let TargetPrefix = "riscv" in
+def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+
 // Vendor extensions
 //===----------------------------------------------------------------------===//
 include "llvm/IR/IntrinsicsRISCVXTHead.td"

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -2198,6 +2198,14 @@ def : Pat<(binop_allwusers<add> GPR:$rs1, immop_oneuse<AddiPair>:$rs2),
 def : Pat<(i64 (add GPR:$rs1, negImm:$rs2)), (SUB GPR:$rs1, negImm:$rs2)>;
 }
 
+//===----------------------------------------------------------------------===//
+// Zihintpause
+//===----------------------------------------------------------------------===//
+
+// Zihintpause
+let Predicates = [HasStdExtZihintpause] in
+def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>;
+
 //===----------------------------------------------------------------------===//
 // Standard extensions
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/RISCV/riscv-zihintpause.ll

@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+zihintpause -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RVPAUSE
+
+declare void @llvm.riscv.pause()
+
+define void @test_pause() {
+; RVPAUSE-LABEL: test_pause:
+; RVPAUSE:       # %bb.0:
+; RVPAUSE-NEXT:    pause
+; RVPAUSE-NEXT:    ret
+  call void @llvm.riscv.pause()
+  ret void
+}