[BOLT] [PowerPC] Port

bolt/CMakeLists.txt

@@ -62,7 +62,7 @@ endif() # standalone
 
 # Determine default set of targets to build -- the intersection of
 # those BOLT supports and those LLVM is targeting.
-set(BOLT_TARGETS_TO_BUILD_all "AArch64;X86;RISCV")
+set(BOLT_TARGETS_TO_BUILD_all "AArch64;X86;RISCV;PowerPC")
 set(BOLT_TARGETS_TO_BUILD_default)
 foreach (tgt ${BOLT_TARGETS_TO_BUILD_all})
   if (tgt IN_LIST LLVM_TARGETS_TO_BUILD)

bolt/include/bolt/Core/BinaryContext.h

@@ -866,6 +866,11 @@ class BinaryContext {
            TheTriple->getArch() == llvm::Triple::x86_64;
   }
 
+  bool isPPC64() const {
+    return TheTriple->getArch() == llvm::Triple::ppc64 ||
+           TheTriple->getArch() == llvm::Triple::ppc64le;
+  }
+
   bool isRISCV() const { return TheTriple->getArch() == llvm::Triple::riscv64; }
 
   // AArch64-specific functions to check if symbol is used to delimit

bolt/include/bolt/Core/MCPlusBuilder.h

@@ -1313,6 +1313,8 @@ class MCPlusBuilder {
     return isCall(Inst) && getEHInfo(Inst);
   }
 
+  virtual bool isTOCRestoreAfterCall(const MCInst &Inst) const { return false; }
+
   /// Return true if \p Inst is an instruction that potentially traps when
   /// working with addresses not aligned to the size of the operand.
   virtual bool requiresAlignedAddress(const MCInst &Inst) const {
@@ -2373,6 +2375,11 @@ MCPlusBuilder *createRISCVMCPlusBuilder(const MCInstrAnalysis *,
                                         const MCRegisterInfo *,
                                         const MCSubtargetInfo *);
 
+MCPlusBuilder *createPowerPCMCPlusBuilder(const MCInstrAnalysis *,
+                                          const MCInstrInfo *,
+                                          const MCRegisterInfo *,
+                                          const MCSubtargetInfo *);
+
 } // namespace bolt
 } // namespace llvm
 

bolt/include/bolt/Rewrite/RewriteInstance.h

@@ -283,6 +283,9 @@ class RewriteInstance {
   /// is the expected .plt \p Section entry function size.
   void disassemblePLTSectionX86(BinarySection &Section, uint64_t EntrySize);
 
+  /// Disassemble ppc64-specific .plt \p Section auxiliary function
+  void disassemblePLTSectionPPC64(BinarySection &Section);
+
   /// Disassemble riscv-specific .plt \p Section auxiliary function
   void disassemblePLTSectionRISCV(BinarySection &Section);
 
@@ -514,6 +517,14 @@ class RewriteInstance {
   /// Flag indicating runtime library linking just started.
   bool StartLinkingRuntimeLib{false};
 
+  /// PPC64 TOC (Table of Contents) base address used for resolving function and
+  /// data references on PPC64 binaries. Set when processing PPC64 binaries with
+  /// a TOC base present.
+  uint64_t PPC64TOCBase = 0;
+
+  /// Flag indicating whether PPC64TOCBase has been set and is valid for use.
+  bool HavePPC64TOCBase = false;
+
   /// Information on special Procedure Linkage Table sections. There are
   /// multiple variants generated by different linkers.
   struct PLTSectionInfo {

bolt/include/bolt/Target/PowerPC/PPCMCPlusBuilder.h

@@ -0,0 +1,81 @@
+#pragma once
+
+#include "bolt/Core/MCPlusBuilder.h"
+
+namespace llvm {
+namespace bolt {
+
+class PPCMCPlusBuilder : public MCPlusBuilder {
+public:
+  using MCPlusBuilder::MCPlusBuilder;
+
+  static void createPushRegisters(MCInst &Inst1, MCInst &Inst2, MCPhysReg Reg1,
+                                  MCPhysReg Reg2);
+
+  bool shouldRecordCodeRelocation(unsigned Type) const override;
+
+  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
+                      uint64_t &Target) const override;
+
+  bool evaluateMemOperandTarget(const MCInst &Inst, uint64_t &Target,
+                                uint64_t Address = 0,
+                                uint64_t Size = 0) const override;
+  bool hasPCRelOperand(const MCInst &I) const override;
+  int getPCRelOperandNum(const MCInst &Inst) const;
+
+  int getMemoryOperandNo(const MCInst &Inst) const override;
+
+  void replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
+                           MCContext *Ctx) const override;
+  bool isIndirectBranch(const MCInst &I) const override;
+
+  const MCSymbol *getTargetSymbol(const MCInst &Inst,
+                                  unsigned OpNum = 0) const override;
+
+  bool convertJmpToTailCall(MCInst &Inst) override;
+
+  bool isCall(const MCInst &Inst) const override;
+
+  bool isBranch(const MCInst &Inst) const override;
+
+  bool isTailCall(const MCInst &Inst) const;
+  bool isReturn(const MCInst &Inst) const override;
+  bool isConditionalBranch(const MCInst &Inst) const override;
+  bool isUnconditionalBranch(const MCInst &Inst) const override;
+
+  const MCInst *getConditionalTailCall(const MCInst &Inst) const;
+
+  IndirectBranchType
+  analyzeIndirectBranch(MCInst &Instruction, InstructionIterator Begin,
+                        InstructionIterator End, const unsigned PtrSize,
+                        MCInst *&MemLocInstrOut, unsigned &BaseRegNumOut,
+                        unsigned &IndexRegNumOut, int64_t &DispValueOut,
+                        const MCExpr *&DispExprOut, MCInst *&PCRelBaseOut,
+                        MCInst *&FixedEntryLoadInstr) const override;
+
+  bool isNoop(const MCInst &Inst) const override;
+  void createNoop(MCInst &Nop) const override;
+
+  bool analyzeBranch(InstructionIterator Begin, InstructionIterator End,
+                     const llvm::MCSymbol *&Tgt,
+                     const llvm::MCSymbol *&Fallthrough, llvm::MCInst *&CondBr,
+                     llvm::MCInst *&UncondBr) const override;
+
+  bool lowerTailCall(llvm::MCInst &Inst) override;
+
+  uint64_t analyzePLTEntry(MCInst &Instruction, InstructionIterator Begin,
+                           InstructionIterator End,
+                           uint64_t BeginPC) const override;
+
+  void createLongTailCall(std::vector<MCInst> &Seq, const MCSymbol *Target,
+                          MCContext *Ctx) override;
+
+  std::optional<Relocation>
+  createRelocation(const MCFixup &Fixup,
+                   const MCAsmBackend &MAB) const override;
+
+  bool isTOCRestoreAfterCall(const MCInst &I) const override;
+};
+
+} // namespace bolt
+} // namespace llvm

bolt/lib/Core/BinaryContext.cpp

@@ -182,6 +182,20 @@ Expected<std::unique_ptr<BinaryContext>> BinaryContext::createBinaryContext(
     ArchName = "aarch64";
     FeaturesStr = "+all";
     break;
+  case llvm::Triple::ppc64:
+    if (Features)
+      return createFatalBOLTError(
+          "PowerPC target does not use SubtargetFeatures");
+    ArchName = "ppc64";
+    FeaturesStr = "";
+    break;
+  case llvm::Triple::ppc64le:
+    if (Features)
+      return createFatalBOLTError(
+          "PowerPC target does not use SubtargetFeatures");
+    ArchName = "ppc64le";
+    FeaturesStr = "";
+    break;
   case llvm::Triple::riscv64: {
     ArchName = "riscv64";
     if (!Features)

bolt/lib/Core/BinaryEmitter.cpp

@@ -26,6 +26,8 @@
 #include "llvm/Support/SMLoc.h"
 
 #define DEBUG_TYPE "bolt"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 using namespace bolt;
@@ -471,10 +473,24 @@ void BinaryEmitter::emitFunctionBody(BinaryFunction &BF, FunctionFragment &FF,
         Streamer.emitLabel(EntrySymbol);
     }
 
+    bool LastWasCall = false;
     SMLoc LastLocSeen;
     for (auto I = BB->begin(), E = BB->end(); I != E; ++I) {
       MCInst &Instr = *I;
 
+      // PPC64 ELFv2: JITLink expects a NOP at call+4 and will rewrite it to
+      // 'ld r2,24(r1)'. The static linker already emits the  LD and then
+      // JITLink asserts that it expects NOP at call+4. Normalise here so
+      // JITLink doesn't assert.
+      if (BC.isPPC64() && LastWasCall && BC.MIB->isTOCRestoreAfterCall(Instr)) {
+        LLVM_DEBUG(dbgs() << "PPC emit: normalizing TOC-restore after call\n");
+        MCInst Nop;
+        BC.MIB->createNoop(Nop); // ori r0,r0,0
+        Streamer.emitInstruction(Nop, *BC.STI);
+        LastWasCall = false;
+        continue;
+      }
+
       if (EmitCodeOnly && BC.MIB->isPseudo(Instr))
         continue;
 
@@ -519,7 +535,49 @@ void BinaryEmitter::emitFunctionBody(BinaryFunction &BF, FunctionFragment &FF,
         }
       }
 
+      LLVM_DEBUG(dbgs() << "EMIT " << BC.MII->getName(Instr.getOpcode())
+                        << "\n");
+
       Streamer.emitInstruction(Instr, *BC.STI);
+      LastWasCall = BC.MIB->isCall(Instr);
+
+      if (BC.isPPC64() && BC.MIB->isTOCRestoreAfterCall(Instr))
+        LLVM_DEBUG(dbgs() << "EMIT is TOC-restore\n");
+
+      // --- PPC64 ELFv2: guarantee a post-call NOP (call slot)
+      if (BC.isPPC64() && BC.MIB->isCall(Instr)) {
+        bool NeedSlot = true;
+        LLVM_DEBUG(dbgs() << "PPC emit: call, considering slot after\n");
+
+        // If the next IR instruction exists and is already a NOP or TOC-restore
+        // , don't inject.
+        auto NextI = std::next(I);
+        LLVM_DEBUG({
+          dbgs() << "PPC emit: CALL seen: next=";
+          if (NextI == E)
+            dbgs() << "<end>\n";
+          else
+            dbgs() << BC.MII->getName(NextI->getOpcode())
+                   << (BC.MIB->isTOCRestoreAfterCall(*NextI)
+                           ? " (TOC restore)\n"
+                           : "\n");
+        });
+        if (NextI != E &&
+            (BC.MIB->isNoop(*NextI) || BC.MIB->isTOCRestoreAfterCall(*NextI))) {
+          NeedSlot = false;
+        }
+
+        if (NeedSlot) {
+          LLVM_DEBUG(dbgs() << "PPC emit: inserting post-call NOP\n");
+          MCInst N;
+          BC.MIB->createNoop(N);
+          Streamer.emitInstruction(N, *BC.STI);
+          LLVM_DEBUG(dbgs() << "PPC: inserted NOP after call at "
+                            << BF.getPrintName() << "\n");
+        } else {
+          LLVM_DEBUG(dbgs() << "PPC emit: post-call NOP not needed\n");
+        }
+      }
     }
   }
 

bolt/lib/Core/BinaryFunction.cpp

@@ -1367,6 +1367,7 @@ Error BinaryFunction::disassemble() {
       setIgnored();
 
     if (MIB->isBranch(Instruction) || MIB->isCall(Instruction)) {
+
       uint64_t TargetAddress = 0;
       if (MIB->evaluateBranch(Instruction, AbsoluteInstrAddr, Size,
                               TargetAddress)) {