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[PowerPC ][NFC] Add a test case for the function atomic_compare_exchange_weak #141263

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Merged
merged 5 commits into from
May 27, 2025
Merged

[PowerPC ][NFC] Add a test case for the function atomic_compare_exchange_weak #141263

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7bc1741
add a NFC test case for the function atomic_compare_exchange_weak
diggerlin May 23, 2025
6578688
minor change
diggerlin May 23, 2025
49682c5
Update llvm/test/CodeGen/PowerPC/atomic-compare-exchange-weak.ll
diggerlin May 26, 2025
3f808ca
address comment
diggerlin May 26, 2025
9d92539
run utils/update_llc_test_checks.py
diggerlin May 27, 2025
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100 changes: 100 additions & 0 deletions llvm/test/CodeGen/PowerPC/atomic-compare-exchange-weak.ll
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; Test the generation of asm for the function:
; int foo(_Atomic int *cp, int *old, int c) {
; return atomic_compare_exchange_weak_explicit(cp, old, c, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
; }

; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix -mcpu=pwr8 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
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@amy-kwan amy-kwan May 26, 2025

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nit: split the run lines since they seem too long

; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix -mcpu=pwr8 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK64
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@lei137 lei137 May 26, 2025

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should also use -ppc-vsr-nums-as-vr
Can we auto generate the checks via utils/update_llc_test_checks.py? It would make it easier if things change. Otherwise we need to better document exactly what is the important part of the code gen that we want to focus on.

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@diggerlin diggerlin May 27, 2025 •
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should also use -ppc-vsr-nums-as-vr

I do not think we need the option since there is no vsr related instructions in the test case.

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@lei137 lei137 May 27, 2025

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that's fair


define i32 @foo(ptr noundef %cp, ptr noundef %old, i32 noundef %c) {
entry:
%cp.addr = alloca ptr, align 4
%old.addr = alloca ptr, align 4
%c.addr = alloca i32, align 4
%.atomictmp = alloca i32, align 4
%cmpxchg.bool = alloca i8, align 1
store ptr %cp, ptr %cp.addr, align 4
store ptr %old, ptr %old.addr, align 4
store i32 %c, ptr %c.addr, align 4
%0 = load ptr, ptr %cp.addr, align 4
%1 = load ptr, ptr %old.addr, align 4
%2 = load i32, ptr %c.addr, align 4
store i32 %2, ptr %.atomictmp, align 4
%3 = load i32, ptr %1, align 4
%4 = load i32, ptr %.atomictmp, align 4
%5 = cmpxchg weak ptr %0, i32 %3, i32 %4 monotonic monotonic, align 4
%6 = extractvalue { i32, i1 } %5, 0
%7 = extractvalue { i32, i1 } %5, 1
br i1 %7, label %cmpxchg.continue, label %cmpxchg.store_expected

cmpxchg.store_expected: ; preds = %entry
store i32 %6, ptr %1, align 4
br label %cmpxchg.continue

cmpxchg.continue: ; preds = %cmpxchg.store_expected, %entry
%storedv = zext i1 %7 to i8
store i8 %storedv, ptr %cmpxchg.bool, align 1
%8 = load i8, ptr %cmpxchg.bool, align 1
%loadedv = trunc i8 %8 to i1
%conv = zext i1 %loadedv to i32
ret i32 %conv
}

; CHECK: .foo:
; CHECK-NEXT: # %bb.0: # %entry
; CHECK-NEXT: lwz r7, 0(r4)
; CHECK-NEXT: stw r3, -4(r1)
; CHECK-NEXT: stw r4, -8(r1)
; CHECK-NEXT: stw r5, -12(r1)
; CHECK-NEXT: stw r5, -16(r1)
; CHECK-NEXT: L..BB0_1: # %entry
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lwarx r6, 0, r3
; CHECK-NEXT: cmpw cr1, r6, r7
; CHECK-NEXT: bne cr1, L..BB0_3
; CHECK-NEXT: # %bb.2: # %entry
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: stwcx. r5, 0, r3
; CHECK-NEXT: bne cr0, L..BB0_1
; CHECK-NEXT: L..BB0_3: # %entry
; CHECK-NEXT: cmplw r6, r7
; CHECK-NEXT: beq cr0, L..BB0_5
; CHECK-NEXT: # %bb.4: # %cmpxchg.store_expected
; CHECK-NEXT: stw r6, 0(r4)
; CHECK-NEXT: L..BB0_5: # %cmpxchg.continue
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: li r4, 1
; CHECK-NEXT: isel r3, r4, r3, 4*cr1+eq
; CHECK-NEXT: stb r3, -17(r1)
; CHECK-NEXT: blr

; CHECK64: .foo:
; CHECK64-NEXT: # %bb.0: # %entry
; CHECK64-NEXT: lwz r7, 0(r4)
; CHECK64-NEXT: std r3, -8(r1)
; CHECK64-NEXT: std r4, -16(r1)
; CHECK64-NEXT: stw r5, -20(r1)
; CHECK64-NEXT: stw r5, -24(r1)
; CHECK64-NEXT: L..BB0_1: # %entry
; CHECK64-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK64-NEXT: lwarx r6, 0, r3
; CHECK64-NEXT: cmpw cr1, r6, r7
; CHECK64-NEXT: bne cr1, L..BB0_3
; CHECK64-NEXT: # %bb.2: # %entry
; CHECK64-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK64-NEXT: stwcx. r5, 0, r3
; CHECK64-NEXT: bne cr0, L..BB0_1
; CHECK64-NEXT: L..BB0_3: # %entry
; CHECK64-NEXT: cmplw r6, r7
; CHECK64-NEXT: beq cr0, L..BB0_5
; CHECK64-NEXT: # %bb.4: # %cmpxchg.store_expected
; CHECK64-NEXT: stw r6, 0(r4)
; CHECK64-NEXT: L..BB0_5: # %cmpxchg.continue
; CHECK64-NEXT: li r3, 0
; CHECK64-NEXT: li r4, 1
; CHECK64-NEXT: isel r3, r4, r3, 4*cr1+eq
; CHECK64-NEXT: li r4, 1
; CHECK64-NEXT: stb r3, -25(r1)
; CHECK64-NEXT: li r3, 0
; CHECK64-NEXT: isel r3, r4, r3, 4*cr1+eq
; CHECK64-NEXT: blr