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@simonzgx simonzgx commented May 26, 2025

Fixes #140639

@llvmbot llvmbot added the llvm:SelectionDAG SelectionDAGISel as well label May 26, 2025
@simonzgx simonzgx marked this pull request as draft May 26, 2025 11:19
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llvmbot commented May 26, 2025

@llvm/pr-subscribers-backend-x86
@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-backend-loongarch

@llvm/pr-subscribers-llvm-selectiondag

Author: Xu Zhang (simonzgx)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/141476.diff

1 Files Affected:

  • (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+7)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index efaa8bd4a7950..31fbab23e4fcf 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7528,6 +7528,13 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
       return DAG.getNode(ISD::AND, DL, VT, X,
                          DAG.getNOT(DL, DAG.getNode(Opc, DL, VT, Y, Z), VT));
 
+  // a bitwiseop (~b + c) -> a bitwiseop ~(b - c).
+  // Fold (and X, (add (not Y), Z)) -> (and X, (not (sub Y, Z)))
+  if (sd_match(N, m_And(m_Value(X), m_Add(m_Value(NotY), m_Value(Z)))) &&
+      sd_match(NotY, m_Not(m_Value(Y))) &&
+      (TLI.hasAndNot(SDValue(N, 0)) || NotY->hasOneUse())) {
+		return DAG.getNode(ISD::AND, DL, VT, X, DAG.getNOT(DL, DAG.getNode(ISD::SUB, DL, VT, Y, Z), VT));
+  }
   // Fold (and (srl X, C), 1) -> (srl X, BW-1) for signbit extraction
   // If we are shifting down an extended sign bit, see if we can simplify
   // this to shifting the MSB directly to expose further simplifications.

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github-actions bot commented May 26, 2025

✅ With the latest revision this PR passed the C/C++ code formatter.

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jayfoad commented May 27, 2025

As well as ~y+z --> ~(y-z) you can also do ~y-z --> ~(y+z) right?

@RKSimon RKSimon requested review from RKSimon, arsenm and jayfoad May 27, 2025 11:11
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Needs tests

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Needs tests

Yes, there are some failed UT that need fixing and some new ones to add. I'm still working on both and will submit soon.

@simonzgx simonzgx changed the title [WIP] Fold (bitwiseop X, (add (not Y), Z)) -> (bitwiseop X, (not (sub Y, Z))). [DAG] Fold (bitwiseop X, (add (not Y), Z)) -> (bitwiseop X, (not (sub Y, Z))). May 29, 2025
@simonzgx simonzgx marked this pull request as ready for review May 29, 2025 11:10
@simonzgx simonzgx requested review from RKSimon and arsenm May 29, 2025 11:11
@simonzgx simonzgx changed the title [DAG] Fold (bitwiseop X, (add (not Y), Z)) -> (bitwiseop X, (not (sub Y, Z))). [DAG] Fold (and X, (add (not Y), Z)) -> (and X, (not (sub Y, Z))). Jun 2, 2025
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pin


if (sd_match(N, m_BitwiseLogic(m_Value(X),
m_Sub(m_AllOf(m_Value(Y), m_Not(m_Value(Y)),
m_OneUse(m_Not(m_Value(Y)))),
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The m_OneUse isn't doing anything as the previous pattern is matching all m_Not cases

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Please can regenerate the failing test files:
LLVM :: CodeGen/LoongArch/ctlz-cttz-ctpop.ll
LLVM :: CodeGen/X86/vector-lzcnt-128.ll

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LGTM - cheers!

@RKSimon RKSimon merged commit 7c25db3 into llvm:main Jun 16, 2025
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akuhlens pushed a commit to akuhlens/llvm-project that referenced this pull request Jun 24, 2025
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a & ~(a - b) optimizes to a & (~a + b) even though most targets have an ANDN instruction

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