[RISCV] Add support for -mtune=andes-45-series #142900
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Enables the use of `-mtune=andes-45-series` to generate code optimized with the Andes 45 series scheduling model and tuning features.
llvmbot
added
clang
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@llvm/pr-subscribers-clang Author: Jim Lin (tclin914) ChangesEnables the use of Full diff: https://github.com/llvm/llvm-project/pull/142900.diff 3 Files Affected:
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 66952755e9159..d736695b48835 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -77,6 +77,7 @@
// TUNE-RISCV32-SAME: {{^}}, syntacore-scr3-rv32
// TUNE-RISCV32-SAME: {{^}}, syntacore-scr4-rv32
// TUNE-RISCV32-SAME: {{^}}, syntacore-scr5-rv32
+// TUNE-RISCV32-SAME: {{^}}, andes-45-series
// TUNE-RISCV32-SAME: {{^}}, generic
// TUNE-RISCV32-SAME: {{^}}, generic-ooo
// TUNE-RISCV32-SAME: {{^}}, rocket
@@ -114,6 +115,7 @@
// TUNE-RISCV64-SAME: {{^}}, veyron-v1
// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
+// TUNE-RISCV64-SAME: {{^}}, andes-45-series
// TUNE-RISCV64-SAME: {{^}}, generic
// TUNE-RISCV64-SAME: {{^}}, generic-ooo
// TUNE-RISCV64-SAME: {{^}}, rocket
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 7d734f2e258e6..73f9f8db425ba 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -209,6 +209,7 @@ Changes to the RISC-V Backend
* `-mcpu=andes-a25` and `-mcpu=andes-ax25` were added.
* The `Shlcofideleg` extension was added.
* `-mcpu=sifive-x390` was added.
+* `-mtune=andes-45-series` was added.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index cfc0957ea88f8..de6f0ecfce737 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -722,6 +722,9 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
FeatureStdExtZbc,
FeatureVendorXAndesPerf]>;
+def ANDES_45 : RISCVTuneProcessorModel<"andes-45-series",
+ Andes45Model>;
+
def ANDES_N45 : RISCVProcessorModel<"andes-n45",
Andes45Model,
[Feature32Bit,
|
Member
|
@llvm/pr-subscribers-backend-risc-v Author: Jim Lin (tclin914) ChangesEnables the use of Full diff: https://github.com/llvm/llvm-project/pull/142900.diff 3 Files Affected:
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 66952755e9159..d736695b48835 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -77,6 +77,7 @@
// TUNE-RISCV32-SAME: {{^}}, syntacore-scr3-rv32
// TUNE-RISCV32-SAME: {{^}}, syntacore-scr4-rv32
// TUNE-RISCV32-SAME: {{^}}, syntacore-scr5-rv32
+// TUNE-RISCV32-SAME: {{^}}, andes-45-series
// TUNE-RISCV32-SAME: {{^}}, generic
// TUNE-RISCV32-SAME: {{^}}, generic-ooo
// TUNE-RISCV32-SAME: {{^}}, rocket
@@ -114,6 +115,7 @@
// TUNE-RISCV64-SAME: {{^}}, veyron-v1
// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
+// TUNE-RISCV64-SAME: {{^}}, andes-45-series
// TUNE-RISCV64-SAME: {{^}}, generic
// TUNE-RISCV64-SAME: {{^}}, generic-ooo
// TUNE-RISCV64-SAME: {{^}}, rocket
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 7d734f2e258e6..73f9f8db425ba 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -209,6 +209,7 @@ Changes to the RISC-V Backend
* `-mcpu=andes-a25` and `-mcpu=andes-ax25` were added.
* The `Shlcofideleg` extension was added.
* `-mcpu=sifive-x390` was added.
+* `-mtune=andes-45-series` was added.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index cfc0957ea88f8..de6f0ecfce737 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -722,6 +722,9 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
FeatureStdExtZbc,
FeatureVendorXAndesPerf]>;
+def ANDES_45 : RISCVTuneProcessorModel<"andes-45-series",
+ Andes45Model>;
+
def ANDES_N45 : RISCVProcessorModel<"andes-n45",
Andes45Model,
[Feature32Bit,
|
wangpc-pp
approved these changes
Jun 5, 2025
lenary
approved these changes
Jun 5, 2025
mshockwave
approved these changes
Jun 5, 2025
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/3/builds/17084 Here is the relevant piece of the build log for the reference |
Contributor
Author
I’m not sure why the test fails to find the string andes-45-series, since it works fine on my local machine. |
Member
I also noticed that the this specific buildbot, arc-builder, tends to throw confusing errors like this when we added a new |
Collaborator
|
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Enables the use of
-mtune=andes-45-seriesto generate code optimized withthe Andes 45 series scheduling model and tuning features.