[SelectionDAG] Allow vselect in foldBinOpIntoSelect #143283
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@llvm/pr-subscribers-backend-x86 Author: AZero13 (AZero13) ChangesIt seems vselect was also meant to be an option given the comment and the fact vectors are allowed and the kind is checked too. Full diff: https://github.com/llvm/llvm-project/pull/143283.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index aba3c0f80a024..a00d09becee74 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2490,7 +2490,8 @@ SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
unsigned SelOpNo = 0;
SDValue Sel = BO->getOperand(0);
auto BinOpcode = BO->getOpcode();
- if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
+ if ((Sel.getOpcode() != ISD::SELECT && Sel.getOpcode() != ISD::VSELECT) ||
+ !Sel.hasOneUse()) {
SelOpNo = 1;
Sel = BO->getOperand(1);
@@ -2506,7 +2507,8 @@ SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
}
}
- if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
+ if ((Sel.getOpcode() != ISD::SELECT && Sel.getOpcode() != ISD::VSELECT) ||
+ !Sel.hasOneUse())
return SDValue();
SDValue CT = Sel.getOperand(1);
diff --git a/llvm/test/CodeGen/X86/extract-vselect-setcc.ll b/llvm/test/CodeGen/X86/extract-vselect-setcc.ll
index 96c8e773d5edd..eff130b25dfab 100644
--- a/llvm/test/CodeGen/X86/extract-vselect-setcc.ll
+++ b/llvm/test/CodeGen/X86/extract-vselect-setcc.ll
@@ -5,11 +5,11 @@ define void @PR117684(i1 %cond, <8 x float> %vec, ptr %ptr1, ptr %ptr2) #0 {
; CHECK-LABEL: PR117684:
; CHECK: # %bb.0:
; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vcmpnltss %xmm1, %xmm0, %k1
-; CHECK-NEXT: vbroadcastss {{.*#+}} xmm0 = [NaN,NaN,NaN,NaN]
-; CHECK-NEXT: vinsertf32x4 $0, %xmm0, %ymm0, %ymm0 {%k1} {z}
-; CHECK-NEXT: vmulss %xmm1, %xmm0, %xmm0
-; CHECK-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [NaN,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vcmpltss %xmm1, %xmm0, %k1
+; CHECK-NEXT: vmovaps %xmm2, %xmm0
+; CHECK-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
+; CHECK-NEXT: vmulss %xmm2, %xmm0, %xmm2
; CHECK-NEXT: vbroadcastss %xmm2, %ymm2
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: cmoveq %rdx, %rsi
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Member
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@llvm/pr-subscribers-llvm-selectiondag Author: AZero13 (AZero13) ChangesIt seems vselect was also meant to be an option given the comment and the fact vectors are allowed and the kind is checked too. Full diff: https://github.com/llvm/llvm-project/pull/143283.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index aba3c0f80a024..a00d09becee74 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2490,7 +2490,8 @@ SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
unsigned SelOpNo = 0;
SDValue Sel = BO->getOperand(0);
auto BinOpcode = BO->getOpcode();
- if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
+ if ((Sel.getOpcode() != ISD::SELECT && Sel.getOpcode() != ISD::VSELECT) ||
+ !Sel.hasOneUse()) {
SelOpNo = 1;
Sel = BO->getOperand(1);
@@ -2506,7 +2507,8 @@ SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
}
}
- if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
+ if ((Sel.getOpcode() != ISD::SELECT && Sel.getOpcode() != ISD::VSELECT) ||
+ !Sel.hasOneUse())
return SDValue();
SDValue CT = Sel.getOperand(1);
diff --git a/llvm/test/CodeGen/X86/extract-vselect-setcc.ll b/llvm/test/CodeGen/X86/extract-vselect-setcc.ll
index 96c8e773d5edd..eff130b25dfab 100644
--- a/llvm/test/CodeGen/X86/extract-vselect-setcc.ll
+++ b/llvm/test/CodeGen/X86/extract-vselect-setcc.ll
@@ -5,11 +5,11 @@ define void @PR117684(i1 %cond, <8 x float> %vec, ptr %ptr1, ptr %ptr2) #0 {
; CHECK-LABEL: PR117684:
; CHECK: # %bb.0:
; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vcmpnltss %xmm1, %xmm0, %k1
-; CHECK-NEXT: vbroadcastss {{.*#+}} xmm0 = [NaN,NaN,NaN,NaN]
-; CHECK-NEXT: vinsertf32x4 $0, %xmm0, %ymm0, %ymm0 {%k1} {z}
-; CHECK-NEXT: vmulss %xmm1, %xmm0, %xmm0
-; CHECK-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [NaN,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vcmpltss %xmm1, %xmm0, %k1
+; CHECK-NEXT: vmovaps %xmm2, %xmm0
+; CHECK-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
+; CHECK-NEXT: vmulss %xmm2, %xmm0, %xmm2
; CHECK-NEXT: vbroadcastss %xmm2, %ymm2
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: cmoveq %rdx, %rsi
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It seems vselect was also meant to be an option given the comment and the fact vectors are allowed and the kind is checked too.
Contributor
Author
|
@RKSimon thoughts? |
topperc
reviewed
Aug 7, 2025
| if (Select.getOpcode() != ISD::SELECT && Select.getOpcode() != ISD::VSELECT) | ||
| std::swap(Select, X); | ||
|
|
||
| SDValue Cond = Select.getOperand(0); |
Collaborator
There was a problem hiding this comment.
Don't the checks for ConstantFPSDNode right below this prevent this from doing anything for VSELECT? ConstantFPSDNode is only used for scalars.
| // fold (fmul X, (select (fcmp X > 0.0), 1.0, -1.0)) -> (fabs X) | ||
| if (Flags.hasNoNaNs() && Flags.hasNoSignedZeros() && | ||
| (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) && | ||
| (N0.getOpcode() == ISD::SELECT || N0.getOpcode() == ISD::VSELECT || |
Collaborator
There was a problem hiding this comment.
This code isn't in the function this PR title references.
RKSimon
requested changes
Aug 15, 2025
| // fold (zext (select cond, c1, c2)) -> (select cond, zext c1, zext c2) | ||
| // fold (aext (select cond, c1, c2)) -> (select cond, sext c1, sext c2) | ||
| if (N0->getOpcode() == ISD::SELECT) { | ||
| if (N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) { |
Collaborator
There was a problem hiding this comment.
Split this and the fmul negation changes into their own patches with test coverage
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It seems vselect was also meant to be an option given the comment and the fact vectors are allowed and the kind is checked too.