[RISCV] Remove fixed vector constraint on masked interleave costing #150624
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The last of the fixed vector changes for interleaves with masked loads and stores landed last night, so we no longer need the restriction.
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@llvm/pr-subscribers-backend-risc-v Author: Philip Reames (preames) ChangesThe last of the fixed vector changes for interleaves with masked loads and stores landed last night, so we no longer need the restriction. Note that our costing in LV will nearly always prefer a scalable type, so this is pretty invisible in practice. All the lowering paths are tested directly. Full diff: https://github.com/llvm/llvm-project/pull/150624.diff 1 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 1624f12a102e3..4899cfdc04fd0 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -983,9 +983,7 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost(
// with an adjacent appropriate memory to vlseg/vsseg intrinsics. vlseg/vsseg
// only support masking per-iteration (i.e. condition), not per-segment (i.e.
// gap).
- // TODO: Support masked interleaved access for fixed length vector.
- if ((isa<ScalableVectorType>(VecTy) || !UseMaskForCond) && !UseMaskForGaps &&
- Factor <= TLI->getMaxSupportedInterleaveFactor()) {
+ if (!UseMaskForGaps && Factor <= TLI->getMaxSupportedInterleaveFactor()) {
auto *VTy = cast<VectorType>(VecTy);
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(VTy);
// Need to make sure type has't been scalarized
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@preames #151665 (comment) |
Philip's out of office this week, I think you can just go ahead and land #151665 and add him as co-author if you want |
I see, thanks. |
Now that support for masked loads/stores of interleave groups has landed, we can enable the loop vectorizer to generate masked interleave access where applicable. This improves vectorization in several ways: * Internal predication support: This enables interleave group vectorization for loops with internal control flow predication, provided all members of the group share the same predicate. Gaps in interleave groups are still not efficiently handled by masking, so masking for gaps remains disabled for now. * Tail folding: This allows tail folding of loops with interleave groups by using masking. Without this, vectorized loops with interleaves would fall back to using separate gather/scatter accesses, which can be significantly less efficient. "[RISCV][TTI] Enable masked interleave access for scalable vector (#149981)" was reverted by 5294793 due to triggering an assertion. The issue has been addressed in the patch "[LV] Fix gap mask requirement for interleaved access (#151105)". On the other hand, this patch also enable fixed-length masked interleave access (#150624) since support for fixed-length has also been landed 992118c. --------- Co-authored-by: Philip Reames <[email protected]>
Yep, totally fine. Thanks! |
The last of the fixed vector changes for interleaves with masked loads and stores landed last night, so we no longer need the restriction.
Note that our costing in LV will nearly always prefer a scalable type, so this is pretty invisible in practice. All the lowering paths are tested directly.