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[RISCV] Remove fixed vector constraint on masked interleave costing #150624

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[RISCV] Remove fixed vector constraint on masked interleave costing #150624

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4 changes: 1 addition & 3 deletions llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -983,9 +983,7 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost(
// with an adjacent appropriate memory to vlseg/vsseg intrinsics. vlseg/vsseg
// only support masking per-iteration (i.e. condition), not per-segment (i.e.
// gap).
// TODO: Support masked interleaved access for fixed length vector.
if ((isa<ScalableVectorType>(VecTy) || !UseMaskForCond) && !UseMaskForGaps &&
Factor <= TLI->getMaxSupportedInterleaveFactor()) {
if (!UseMaskForGaps && Factor <= TLI->getMaxSupportedInterleaveFactor()) {
auto *VTy = cast<VectorType>(VecTy);
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(VTy);
// Need to make sure type has't been scalarized
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