[RISCV] Loosen the requirement of shadow stack codegen to Zimop #152251

jaidTw · 2025-08-06T05:21:49Z

Zicfiss (Shadow Stack) instructions are implemented using the encoding space defined in the "Zimop" May-Be-Operations Extension, where the instruction behaviors turn into NOP if Zimop is implemented but the redefining extension does not present.
This means we can safely loosen the codegen requirement of shadow stack to Zimop, in that those processors with Zimop but no Zicfiss can still execute the instructions without problem.

This patch add new pseudo instructions to model MOPs that are expanded into Zicfiss instructios, and change to emit them in the codegen

llvmbot · 2025-08-06T05:22:23Z

@llvm/pr-subscribers-mc

Author: Jesse Huang (jaidTw)

Changes

Zicfiss (Shadow Stack) instructions are implemented using the encoding space defined in the "Zimop" May-Be-Operations Extension, where the instruction behaviors turn into NOP if Zimop is implemented but the redefining extension does not present.
This means we can safely loosen the codegen requirement of shadow stack to Zimop, in that those processors with Zimop but no Zicfiss can still execute the instructions without problem.

This patches

Modify the requirement predicate for shadow stack instructions, setup a new DecoderTableZicfiss32 and favor it over the DecoderTable32, thus they will only be decoded as shadow stack instructions if Zicfiss is specified in the disassembler, and fallback to mop instructions.
Loosen the hardware shadow stack codegen in RISCVFrameLoweriing from checking Zicfiss to Zimop

Full diff: https://github.com/llvm/llvm-project/pull/152251.diff

6 Files Affected:

(modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+3-1)
(modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+4-2)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td (+9-8)
(modified) llvm/test/CodeGen/RISCV/shadowcallstack.ll (+2-2)
(modified) llvm/test/MC/RISCV/compressed-zicfiss.s (+8-8)
(modified) llvm/test/MC/RISCV/zicfiss-valid.s (+17-17)

diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 67cc01e647a04..b981873989f31 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -693,6 +693,8 @@ static constexpr DecoderListEntry DecoderList32[]{
     {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
     {DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
     {DecoderTableXRivos32, XRivosFeatureGroup, "Rivos"},
+    // DecoderTableZicfiss32 must be checked before DecoderTable32.
+    {DecoderTableZicfiss32, {RISCV::FeatureStdExtZicfiss}, "Zicfiss (Shadow stack)"},
     {DecoderTable32, {}, "standard 32-bit instructions"},
     {DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
     {DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
@@ -738,7 +740,7 @@ static constexpr DecoderListEntry DecoderList16[]{
     {DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"},
     // Standard Extensions
     // DecoderTableZicfiss16 must be checked before DecoderTable16.
-    {DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},
+    {DecoderTableZicfiss16, {RISCV::FeatureStdExtZicfiss}, "Zicfiss (Shadow Stack 16-bit)"},
     {DecoderTable16, {}, "standard 16-bit instructions"},
     {DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
     // Zc* instructions incompatible with Zcf or Zcd
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 9fc0d815ceee3..16392510f5e61 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -107,7 +107,7 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
                             const DebugLoc &DL) {
   const auto &STI = MF.getSubtarget<RISCVSubtarget>();
   bool HasHWShadowStack = MF.getFunction().hasFnAttribute("hw-shadow-stack") &&
-                          STI.hasStdExtZicfiss();
+                          STI.hasStdExtZimop();
   bool HasSWShadowStack =
       MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
   if (!HasHWShadowStack && !HasSWShadowStack)
@@ -123,6 +123,7 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
     return;
 
   const RISCVInstrInfo *TII = STI.getInstrInfo();
+  // Prefer HW shadow stack over SW shadow stack.
   if (HasHWShadowStack) {
     BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
     return;
@@ -172,7 +173,7 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
                             const DebugLoc &DL) {
   const auto &STI = MF.getSubtarget<RISCVSubtarget>();
   bool HasHWShadowStack = MF.getFunction().hasFnAttribute("hw-shadow-stack") &&
-                          STI.hasStdExtZicfiss();
+                          STI.hasStdExtZimop();
   bool HasSWShadowStack =
       MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
   if (!HasHWShadowStack && !HasSWShadowStack)
@@ -185,6 +186,7 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
     return;
 
   const RISCVInstrInfo *TII = STI.getInstrInfo();
+  // Prefer HW shadow stack over SW shadow stack.
   if (HasHWShadowStack) {
     BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);
     return;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
index 49a57f86cccd6..9618bf3f6dab9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
@@ -24,7 +24,8 @@ class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> :
 // Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtZicfiss] in {
+let Predicates = [HasStdExtZimop],
+    DecoderNamespace = "Zicfiss" in {
 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
 def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk",
                        "$rs1"> {
@@ -45,28 +46,28 @@ def SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
   let rd = 0b00000;
   let rs1 = 0b00000;
 }
-} // Predicates = [HasStdExtZicfiss]
+} // Predicates = [HasStdExtZimop]
 
-let Predicates = [HasStdExtZicfiss, HasStdExtZcmop],
+let Predicates = [HasStdExtZcmop],
     DecoderNamespace = "Zicfiss" in {
 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
 def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">;
 
 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
 def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">;
-} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop]
+} // Predicates = [HasStdExtZcmop]
 
-let Predicates = [HasStdExtZicfiss] in
+let Predicates = [HasStdExtZimop], DecoderNamespace = "Zicfiss" in
 defm SSAMOSWAP_W  : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">;
 
-let Predicates = [HasStdExtZicfiss, IsRV64] in
+let Predicates = [HasStdExtZimop, IsRV64], DecoderNamespace = "Zicfiss" in
 defm SSAMOSWAP_D  : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;
 
 //===----------------------------------------------------------------------===/
 // Compress Instruction tablegen backend.
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtZicfiss, HasStdExtZcmop] in {
+let Predicates = [HasStdExtZcmop] in {
 def : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>;
 def : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>;
-} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop]
+} // Predicates = [HasStdExtZcmop]
diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
index 03acd9491fed8..cab3d641d49d9 100644
--- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
+++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
@@ -3,9 +3,9 @@
 ; RUN:   | FileCheck %s --check-prefix=RV32
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV64
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfiss < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zimop < %s \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefix=RV32-ZICFISS
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfiss < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zimop < %s \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefix=RV64-ZICFISS
 
 define void @f1() shadowcallstack {
diff --git a/llvm/test/MC/RISCV/compressed-zicfiss.s b/llvm/test/MC/RISCV/compressed-zicfiss.s
index 7d387b257b7b4..acedee587f3e8 100644
--- a/llvm/test/MC/RISCV/compressed-zicfiss.s
+++ b/llvm/test/MC/RISCV/compressed-zicfiss.s
@@ -14,40 +14,40 @@
 
 # CHECK-ASM-AND-OBJ: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspopchk x5
 
 # CHECK-ASM-AND-OBJ: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspopchk t0
 
 # CHECK-ASM-AND-OBJ: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspush x1
 
 # CHECK-ASM-AND-OBJ: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspush ra
 
 # CHECK-ASM-AND-OBJ: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations){{$}}
 c.sspush x1
 
 # CHECK-ASM-AND-OBJ: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations){{$}}
 c.sspush ra
 
 # CHECK-ASM-AND-OBJ: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations){{$}}
 c.sspopchk x5
 
 # CHECK-ASM-AND-OBJ: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations){{$}}
 c.sspopchk t0
diff --git a/llvm/test/MC/RISCV/zicfiss-valid.s b/llvm/test/MC/RISCV/zicfiss-valid.s
index 5b2ab8d326651..376e971116d67 100644
--- a/llvm/test/MC/RISCV/zicfiss-valid.s
+++ b/llvm/test/MC/RISCV/zicfiss-valid.s
@@ -16,87 +16,87 @@
 
 # CHECK-ASM-AND-OBJ: sspopchk ra
 # CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspopchk x1
 
 # CHECK-ASM-AND-OBJ: sspopchk ra
 # CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspopchk ra
 
 # CHECK-ASM-AND-OBJ: sspopchk t0
 # CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspopchk x5
 
 # CHECK-ASM-AND-OBJ: sspopchk t0
 # CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspopchk t0
 
 # CHECK-ASM-AND-OBJ: sspush ra
 # CHECK-ASM: encoding: [0x73,0x40,0x10,0xce]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspush x1
 
 # CHECK-ASM-AND-OBJ: sspush ra
 # CHECK-ASM: encoding: [0x73,0x40,0x10,0xce]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspush ra
 
 # check-asm-and-obj: sspush t0
 # check-asm: encoding: [0x73,0x40,0x50,0xce]
-# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# check-no-ext: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspush x5
 
 # check-asm-and-obj: sspush t0
 # check-asm: encoding: [0x73,0x40,0x50,0xce]
-# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# check-no-ext: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspush t0
 
 # CHECK-ASM-AND-OBJ: ssrdp ra
 # CHECK-ASM: encoding: [0xf3,0x40,0xc0,0xcd]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssrdp ra
 
 # CHECK-ASM-AND-OBJ: ssamoswap.w a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x27,0x14,0x48]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.w a4, ra, (s0)
 
 # CHECK-ASM-AND-OBJ: ssamoswap.w.aq a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4c]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.w.aq a4, ra, (s0)
 
 # CHECK-ASM-AND-OBJ: ssamoswap.w.rl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4a]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.w.rl a4, ra, (s0)
 
 # CHECK-ASM-AND-OBJ: ssamoswap.w.aqrl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4e]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.w.aqrl a4, ra, (s0)
 
 .ifdef RV64
 # CHECK-ASM-AND-OBJ-RV64: ssamoswap.d a4, ra, (s0)
 # CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x48]
-# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.d a4, ra, (s0)
 
 # CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.aq a4, ra, (s0)
 # CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4c]
-# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.d.aq a4, ra, (s0)
 
 # CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.rl a4, ra, (s0)
 # CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4a]
-# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.d.rl a4, ra, (s0)
 
 # CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.aqrl a4, ra, (s0)
 # CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4e]
-# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.d.aqrl a4, ra, (s0)
 .endif

llvmbot · 2025-08-06T05:22:24Z

@llvm/pr-subscribers-backend-risc-v

Author: Jesse Huang (jaidTw)

Changes

Zicfiss (Shadow Stack) instructions are implemented using the encoding space defined in the "Zimop" May-Be-Operations Extension, where the instruction behaviors turn into NOP if Zimop is implemented but the redefining extension does not present.
This means we can safely loosen the codegen requirement of shadow stack to Zimop, in that those processors with Zimop but no Zicfiss can still execute the instructions without problem.

This patches

Modify the requirement predicate for shadow stack instructions, setup a new DecoderTableZicfiss32 and favor it over the DecoderTable32, thus they will only be decoded as shadow stack instructions if Zicfiss is specified in the disassembler, and fallback to mop instructions.
Loosen the hardware shadow stack codegen in RISCVFrameLoweriing from checking Zicfiss to Zimop

Full diff: https://github.com/llvm/llvm-project/pull/152251.diff

6 Files Affected:

(modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+3-1)
(modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+4-2)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td (+9-8)
(modified) llvm/test/CodeGen/RISCV/shadowcallstack.ll (+2-2)
(modified) llvm/test/MC/RISCV/compressed-zicfiss.s (+8-8)
(modified) llvm/test/MC/RISCV/zicfiss-valid.s (+17-17)

diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 67cc01e647a04..b981873989f31 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -693,6 +693,8 @@ static constexpr DecoderListEntry DecoderList32[]{
     {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
     {DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
     {DecoderTableXRivos32, XRivosFeatureGroup, "Rivos"},
+    // DecoderTableZicfiss32 must be checked before DecoderTable32.
+    {DecoderTableZicfiss32, {RISCV::FeatureStdExtZicfiss}, "Zicfiss (Shadow stack)"},
     {DecoderTable32, {}, "standard 32-bit instructions"},
     {DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
     {DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
@@ -738,7 +740,7 @@ static constexpr DecoderListEntry DecoderList16[]{
     {DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"},
     // Standard Extensions
     // DecoderTableZicfiss16 must be checked before DecoderTable16.
-    {DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},
+    {DecoderTableZicfiss16, {RISCV::FeatureStdExtZicfiss}, "Zicfiss (Shadow Stack 16-bit)"},
     {DecoderTable16, {}, "standard 16-bit instructions"},
     {DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
     // Zc* instructions incompatible with Zcf or Zcd
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 9fc0d815ceee3..16392510f5e61 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -107,7 +107,7 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
                             const DebugLoc &DL) {
   const auto &STI = MF.getSubtarget<RISCVSubtarget>();
   bool HasHWShadowStack = MF.getFunction().hasFnAttribute("hw-shadow-stack") &&
-                          STI.hasStdExtZicfiss();
+                          STI.hasStdExtZimop();
   bool HasSWShadowStack =
       MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
   if (!HasHWShadowStack && !HasSWShadowStack)
@@ -123,6 +123,7 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
     return;
 
   const RISCVInstrInfo *TII = STI.getInstrInfo();
+  // Prefer HW shadow stack over SW shadow stack.
   if (HasHWShadowStack) {
     BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
     return;
@@ -172,7 +173,7 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
                             const DebugLoc &DL) {
   const auto &STI = MF.getSubtarget<RISCVSubtarget>();
   bool HasHWShadowStack = MF.getFunction().hasFnAttribute("hw-shadow-stack") &&
-                          STI.hasStdExtZicfiss();
+                          STI.hasStdExtZimop();
   bool HasSWShadowStack =
       MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
   if (!HasHWShadowStack && !HasSWShadowStack)
@@ -185,6 +186,7 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
     return;
 
   const RISCVInstrInfo *TII = STI.getInstrInfo();
+  // Prefer HW shadow stack over SW shadow stack.
   if (HasHWShadowStack) {
     BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);
     return;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
index 49a57f86cccd6..9618bf3f6dab9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
@@ -24,7 +24,8 @@ class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> :
 // Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtZicfiss] in {
+let Predicates = [HasStdExtZimop],
+    DecoderNamespace = "Zicfiss" in {
 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
 def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk",
                        "$rs1"> {
@@ -45,28 +46,28 @@ def SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
   let rd = 0b00000;
   let rs1 = 0b00000;
 }
-} // Predicates = [HasStdExtZicfiss]
+} // Predicates = [HasStdExtZimop]
 
-let Predicates = [HasStdExtZicfiss, HasStdExtZcmop],
+let Predicates = [HasStdExtZcmop],
     DecoderNamespace = "Zicfiss" in {
 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
 def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">;
 
 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
 def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">;
-} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop]
+} // Predicates = [HasStdExtZcmop]
 
-let Predicates = [HasStdExtZicfiss] in
+let Predicates = [HasStdExtZimop], DecoderNamespace = "Zicfiss" in
 defm SSAMOSWAP_W  : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">;
 
-let Predicates = [HasStdExtZicfiss, IsRV64] in
+let Predicates = [HasStdExtZimop, IsRV64], DecoderNamespace = "Zicfiss" in
 defm SSAMOSWAP_D  : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;
 
 //===----------------------------------------------------------------------===/
 // Compress Instruction tablegen backend.
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtZicfiss, HasStdExtZcmop] in {
+let Predicates = [HasStdExtZcmop] in {
 def : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>;
 def : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>;
-} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop]
+} // Predicates = [HasStdExtZcmop]
diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
index 03acd9491fed8..cab3d641d49d9 100644
--- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
+++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
@@ -3,9 +3,9 @@
 ; RUN:   | FileCheck %s --check-prefix=RV32
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV64
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfiss < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zimop < %s \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefix=RV32-ZICFISS
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfiss < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zimop < %s \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefix=RV64-ZICFISS
 
 define void @f1() shadowcallstack {
diff --git a/llvm/test/MC/RISCV/compressed-zicfiss.s b/llvm/test/MC/RISCV/compressed-zicfiss.s
index 7d387b257b7b4..acedee587f3e8 100644
--- a/llvm/test/MC/RISCV/compressed-zicfiss.s
+++ b/llvm/test/MC/RISCV/compressed-zicfiss.s
@@ -14,40 +14,40 @@
 
 # CHECK-ASM-AND-OBJ: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspopchk x5
 
 # CHECK-ASM-AND-OBJ: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspopchk t0
 
 # CHECK-ASM-AND-OBJ: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspush x1
 
 # CHECK-ASM-AND-OBJ: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspush ra
 
 # CHECK-ASM-AND-OBJ: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations){{$}}
 c.sspush x1
 
 # CHECK-ASM-AND-OBJ: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations){{$}}
 c.sspush ra
 
 # CHECK-ASM-AND-OBJ: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations){{$}}
 c.sspopchk x5
 
 # CHECK-ASM-AND-OBJ: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations){{$}}
 c.sspopchk t0
diff --git a/llvm/test/MC/RISCV/zicfiss-valid.s b/llvm/test/MC/RISCV/zicfiss-valid.s
index 5b2ab8d326651..376e971116d67 100644
--- a/llvm/test/MC/RISCV/zicfiss-valid.s
+++ b/llvm/test/MC/RISCV/zicfiss-valid.s
@@ -16,87 +16,87 @@
 
 # CHECK-ASM-AND-OBJ: sspopchk ra
 # CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspopchk x1
 
 # CHECK-ASM-AND-OBJ: sspopchk ra
 # CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspopchk ra
 
 # CHECK-ASM-AND-OBJ: sspopchk t0
 # CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspopchk x5
 
 # CHECK-ASM-AND-OBJ: sspopchk t0
 # CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspopchk t0
 
 # CHECK-ASM-AND-OBJ: sspush ra
 # CHECK-ASM: encoding: [0x73,0x40,0x10,0xce]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspush x1
 
 # CHECK-ASM-AND-OBJ: sspush ra
 # CHECK-ASM: encoding: [0x73,0x40,0x10,0xce]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspush ra
 
 # check-asm-and-obj: sspush t0
 # check-asm: encoding: [0x73,0x40,0x50,0xce]
-# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# check-no-ext: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspush x5
 
 # check-asm-and-obj: sspush t0
 # check-asm: encoding: [0x73,0x40,0x50,0xce]
-# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# check-no-ext: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 sspush t0
 
 # CHECK-ASM-AND-OBJ: ssrdp ra
 # CHECK-ASM: encoding: [0xf3,0x40,0xc0,0xcd]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssrdp ra
 
 # CHECK-ASM-AND-OBJ: ssamoswap.w a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x27,0x14,0x48]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.w a4, ra, (s0)
 
 # CHECK-ASM-AND-OBJ: ssamoswap.w.aq a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4c]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.w.aq a4, ra, (s0)
 
 # CHECK-ASM-AND-OBJ: ssamoswap.w.rl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4a]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.w.rl a4, ra, (s0)
 
 # CHECK-ASM-AND-OBJ: ssamoswap.w.aqrl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4e]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.w.aqrl a4, ra, (s0)
 
 .ifdef RV64
 # CHECK-ASM-AND-OBJ-RV64: ssamoswap.d a4, ra, (s0)
 # CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x48]
-# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.d a4, ra, (s0)
 
 # CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.aq a4, ra, (s0)
 # CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4c]
-# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.d.aq a4, ra, (s0)
 
 # CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.rl a4, ra, (s0)
 # CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4a]
-# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.d.rl a4, ra, (s0)
 
 # CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.aqrl a4, ra, (s0)
 # CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4e]
-# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zimop' (May-Be-Operations){{$}}
 ssamoswap.d.aqrl a4, ra, (s0)
 .endif

github-actions · 2025-08-06T05:24:54Z

✅ With the latest revision this PR passed the C/C++ code formatter.

llvm/test/MC/RISCV/compressed-zicfiss.s

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

jaidTw · 2025-08-20T14:02:02Z

@mylai-mtk I have adopt your suggestion, while I don't see a way to output mop pseudos mnemonics in different form (shadow stack/mop) in assembly based on the presence of Zicfiss, it will still emit the shadow stack variants directly instead of pseudos if Zicfiss is present

mylai-mtk · 2025-08-22T08:59:46Z

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

Hi, thanks for the effort to fill-in all these bits of information, but this is not what I'm expecting. What I was expecting are pure compiler pseudos that are only usable in the compiler pipeline, but not in the assembler/disassembler/... . What you created here are "real" (not pseudo) insns that expands to MOP insns.

What I was expecting to see was something like:

def PseudoMOP_SSPUSH : Pseudo<(outs), (ins GPRX1X5:$ra), []>, PseudoInstExpansion<(MOPRR7 GPRX0, GPRX0, GPRX1X5:$ra)>;

This creates a compiler-only pseudo insn that is only usable in the compiler pipeline, and can be auto-expanded to the correct MOP insn during emission.

By using this methodology, I hope the following could be achieved:

Avoid directly emitting Zicfiss insns for the sake of limiting Zicfiss insns to just Zicfiss infras -> Use pseudo insns instead of Zicfiss insns [v].

Provide a method that allows easy identifying of these insns as Zicfiss insns in the compiler pipeline to facilitate possible future manipulations -> The pseudo insns have their allocated in-compiler insn numbers that are different from those of plain MOP insns so it's easy to identify them in the compiler, e.g RISCV::PseudoMOP_SSPUSH vs RISCV::MOPRR7 [v].

The implementation should be easy to maintain -> The tablegen Pseudo<>, PseudoInstExpansion<> implementation is a one-liner and contains only the necessary information to allow insn instantiation and emission. Most importantly, no bit pattern nor textual format is in it, so we don't need to maintain these information. [v]

So I guess if the tablegen methodology compiles, everything would be fine and the goals be satisfied.

About assemblers/disassemblers, I think supporting these scenarios should be enabled by the real Zicfiss/MOP extension implementations, since users of these tools should have a clear understanding of the ISA he/she is targeting so he/she can deal with those programs written in machine-level insns. This means he/she needs to set the correct ISA extensions when working with these tools, and here (in this PR and thus just the compiler pipeline) all we need to do is just not to break the framework so normal Zicfiss/MOP extension implementations would enable the assemblers and disassemblers to function properly if the ISA extension is enabled.

I was attempting to achieve the compression of sspush -> c.sspush in the pipeline, and that way we would need to carry the encodings in the instructions because there's no mapping between mop and c.mop and that is why I didn't go with the PseudoInstExpansion.
However, I found it seems to be simpler to just determine whether we should compress or not at the emission time. So yeah, why not just changed it back to use PseudoInstExpansion.
I also agree your opinon on the disassembler behavior, I've updated the test accordingly.

mylai-mtk

Given that Zcmop insns are not the compressed form of Zimop insns, it's a pity that with the current infrastructure we could not compress PseudoMOP_SSPUSH with TableGen rules. The formal solution of this would be to create infrastructures of compressing pseudo insns, but I believe that would be a change too big compared with the simple purpose of this patch.

However, I would still like to provide a workaround that is more probable in the near future: Model hardware shadow stack support as a target feature and predicate TableGen CompressPat<MOP, CMOP> based on that target feature. I'm currently modeling Zicfilp CFI as target features, so I now have some ideas about the pros and cons of modeling module flags as target features, which I plan to list out in my PR and link it to here. Nevertheless, I'm OK with the current approach of this PR regarding SSPUSH compression.

By the way, I like the idea of completely replacing Zicfiss SSPUSH with Zimop PseudoMOP_SSPUSH. This consolidates the divergent cases.

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

mylai-mtk · 2025-08-28T03:03:13Z

@jaidTw Looks like you've got a CI failure. Could you take a look at it?

jaidTw · 2025-08-28T05:09:09Z

@jaidTw Looks like you've got a CI failure. Could you take a look at it?

2025-08-28T02:43:44.1309989Z Running runtimes checks requiring reconfiguring targets: check-cxx check-cxxabi check-unwind
2025-08-28T02:43:44.1325123Z sccache: Starting the server...
2025-08-28T02:43:44.1402784Z sccache: error: Cannot open/write log file 'artifacts/sccache.log'
2025-08-28T02:43:54.1426567Z sccache: error: Timed out waiting for server startup
2025-08-28T02:43:54.1460511Z ##[error]Process completed with exit code 2.

Re-running to see if we can get it fixed

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

jaidTw · 2025-09-04T03:12:05Z

Ping

mylai-mtk

LGTM

topperc

LGTM

…mop (#152252) Following #152251 We can now loosen the requirement of `-fcf-protection=return` from Zicfiss to Zimop

…eturn to zimop (#152252) Following llvm/llvm-project#152251 We can now loosen the requirement of `-fcf-protection=return` from Zicfiss to Zimop

jaidTw requested review from kito-cheng, mylai-mtk and topperc August 6, 2025 05:21

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[Clang][RISCV] Loosen the requirement of -fcf-protection=return to zimop #152252

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[RISCV][Zicfilp] Enable Zicfilp CFI compiler behaviors by looking at module flags #152121

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[RISCV] Add underscores to instructions names for Zimop/Zcmop. #155289

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[RISCV] Add Pseudo for MOPs that representing shadow stack insns

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[RISCV] Loosen the requirement of shadow stack codegen to Zimop

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jaidTw merged commit 9bbf22c into llvm:main Sep 9, 2025
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[Clang][RISCV] Loosen the requirement of -fcf-protection=return to zi…

e91f367

…mop (#152252) Following #152251 We can now loosen the requirement of `-fcf-protection=return` from Zicfiss to Zimop

[RISCV] Loosen the requirement of shadow stack codegen to Zimop #152251

[RISCV] Loosen the requirement of shadow stack codegen to Zimop #152251

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