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[RISCV] Loosen the requirement of shadow stack codegen to Zimop #152251

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Merged
merged 2 commits into from
Sep 9, 2025
Merged

[RISCV] Loosen the requirement of shadow stack codegen to Zimop #152251

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17efbfb
[RISCV] Add Pseudo for MOPs that representing shadow stack insns
jaidTw Aug 24, 2025
366e892
[RISCV] Loosen the requirement of shadow stack codegen to Zimop
jaidTw Aug 24, 2025
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19 changes: 15 additions & 4 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -106,8 +106,14 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL) {
const auto &STI = MF.getSubtarget<RISCVSubtarget>();
// We check Zimop instead of (Zimop || Zcmop) to determine whether HW shadow
// stack is available despite the fact that sspush/sspopchk both have a
// compressed form, because if only Zcmop is available, we would need to
// reserve X5 due to c.sspopchk only takes X5 and we currently do not support
// using X5 as the return address register.
// However, we can still aggressively use c.sspush x1 if zcmop is available.
bool HasHWShadowStack = MF.getFunction().hasFnAttribute("hw-shadow-stack") &&
STI.hasStdExtZicfiss();
STI.hasStdExtZimop();
bool HasSWShadowStack =
MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
if (!HasHWShadowStack && !HasSWShadowStack)
Expand All @@ -124,7 +130,12 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,

const RISCVInstrInfo *TII = STI.getInstrInfo();
if (HasHWShadowStack) {
BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
if (STI.hasStdExtZcmop()) {
static_assert(RAReg == RISCV::X1, "C.SSPUSH only accepts X1");
BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoMOP_C_SSPUSH));
} else {
BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoMOP_SSPUSH)).addReg(RAReg);
}
return;
}

Expand Down Expand Up @@ -172,7 +183,7 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
const DebugLoc &DL) {
const auto &STI = MF.getSubtarget<RISCVSubtarget>();
bool HasHWShadowStack = MF.getFunction().hasFnAttribute("hw-shadow-stack") &&
STI.hasStdExtZicfiss();
STI.hasStdExtZimop();
bool HasSWShadowStack =
MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
if (!HasHWShadowStack && !HasSWShadowStack)
Expand All @@ -186,7 +197,7 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,

const RISCVInstrInfo *TII = STI.getInstrInfo();
if (HasHWShadowStack) {
BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);
BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoMOP_SSPOPCHK)).addReg(RAReg);
return;
}

Expand Down
4 changes: 3 additions & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2330,7 +2330,6 @@ include "RISCVInstrInfoZalasr.td"
include "RISCVInstrInfoZimop.td"
include "RISCVInstrInfoZicbo.td"
include "RISCVInstrInfoZicond.td"
include "RISCVInstrInfoZicfiss.td"
include "RISCVInstrInfoZilsd.td"

// Scalar FP
Expand Down Expand Up @@ -2359,6 +2358,9 @@ include "RISCVInstrInfoZc.td"
include "RISCVInstrInfoZcmop.td"
include "RISCVInstrInfoZclsd.td"

// Control Flow Integriy, this requires Zimop/Zcmop
include "RISCVInstrInfoZicfiss.td"

// Short Forward Branch
include "RISCVInstrInfoSFB.td"

Expand Down
15 changes: 15 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
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Expand Up @@ -62,6 +62,21 @@ defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">;
let Predicates = [HasStdExtZicfiss, IsRV64] in
defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;

let Predicates = [HasStdExtZimop] in {
let hasSideEffects = 1, mayLoad = 0, mayStore = 1 in
def PseudoMOP_SSPUSH : Pseudo<(outs), (ins GPRX1X5:$rs2), []>,
PseudoInstExpansion<(MOP_RR_7 X0, X0, GPR:$rs2)>;
let hasSideEffects = 1, mayLoad = 1, mayStore = 0 in
def PseudoMOP_SSPOPCHK : Pseudo<(outs), (ins GPRX1X5:$rs1), []>,
PseudoInstExpansion<(MOP_R_28 X0, GPR:$rs1)>;
} // Predicates = [HasStdExtZimop]

let Predicates = [HasStdExtZcmop] in {
let Uses = [X1], hasSideEffects = 1, mayLoad = 0, mayStore = 1 in
def PseudoMOP_C_SSPUSH : Pseudo<(outs), (ins), []>,
PseudoInstExpansion<(C_MOP_1)>;
} // Predicates = [HasStdExtZcmop]

//===----------------------------------------------------------------------===/
// Compress Instruction tablegen backend.
//===----------------------------------------------------------------------===//
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/shadowcallstack.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -427,7 +427,7 @@ define i32 @f3_hw() "hw-shadow-stack" {
;
; RV32-ZICFISS-LABEL: f3_hw:
; RV32-ZICFISS: # %bb.0:
; RV32-ZICFISS-NEXT: sspush ra
; RV32-ZICFISS-NEXT: mop.rr.7 zero, zero, ra
; RV32-ZICFISS-NEXT: addi sp, sp, -16
; RV32-ZICFISS-NEXT: .cfi_def_cfa_offset 16
; RV32-ZICFISS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
Expand All @@ -437,12 +437,12 @@ define i32 @f3_hw() "hw-shadow-stack" {
; RV32-ZICFISS-NEXT: .cfi_restore ra
; RV32-ZICFISS-NEXT: addi sp, sp, 16
; RV32-ZICFISS-NEXT: .cfi_def_cfa_offset 0
; RV32-ZICFISS-NEXT: sspopchk ra
; RV32-ZICFISS-NEXT: mop.r.28 zero, ra
; RV32-ZICFISS-NEXT: ret
;
; RV64-ZICFISS-LABEL: f3_hw:
; RV64-ZICFISS: # %bb.0:
; RV64-ZICFISS-NEXT: sspush ra
; RV64-ZICFISS-NEXT: mop.rr.7 zero, zero, ra
; RV64-ZICFISS-NEXT: addi sp, sp, -16
; RV64-ZICFISS-NEXT: .cfi_def_cfa_offset 16
; RV64-ZICFISS-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
Expand All @@ -452,7 +452,7 @@ define i32 @f3_hw() "hw-shadow-stack" {
; RV64-ZICFISS-NEXT: .cfi_restore ra
; RV64-ZICFISS-NEXT: addi sp, sp, 16
; RV64-ZICFISS-NEXT: .cfi_def_cfa_offset 0
; RV64-ZICFISS-NEXT: sspopchk ra
; RV64-ZICFISS-NEXT: mop.r.28 zero, ra
; RV64-ZICFISS-NEXT: ret
%res = call i32 @bar()
%res1 = add i32 %res, 1
Expand Down Expand Up @@ -530,7 +530,7 @@ define i32 @f4_hw() "hw-shadow-stack" {
;
; RV32-ZICFISS-LABEL: f4_hw:
; RV32-ZICFISS: # %bb.0:
; RV32-ZICFISS-NEXT: sspush ra
; RV32-ZICFISS-NEXT: mop.rr.7 zero, zero, ra
; RV32-ZICFISS-NEXT: addi sp, sp, -16
; RV32-ZICFISS-NEXT: .cfi_def_cfa_offset 16
; RV32-ZICFISS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
Expand Down Expand Up @@ -561,12 +561,12 @@ define i32 @f4_hw() "hw-shadow-stack" {
; RV32-ZICFISS-NEXT: .cfi_restore s2
; RV32-ZICFISS-NEXT: addi sp, sp, 16
; RV32-ZICFISS-NEXT: .cfi_def_cfa_offset 0
; RV32-ZICFISS-NEXT: sspopchk ra
; RV32-ZICFISS-NEXT: mop.r.28 zero, ra
; RV32-ZICFISS-NEXT: ret
;
; RV64-ZICFISS-LABEL: f4_hw:
; RV64-ZICFISS: # %bb.0:
; RV64-ZICFISS-NEXT: sspush ra
; RV64-ZICFISS-NEXT: mop.rr.7 zero, zero, ra
; RV64-ZICFISS-NEXT: addi sp, sp, -32
; RV64-ZICFISS-NEXT: .cfi_def_cfa_offset 32
; RV64-ZICFISS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
Expand Down Expand Up @@ -597,7 +597,7 @@ define i32 @f4_hw() "hw-shadow-stack" {
; RV64-ZICFISS-NEXT: .cfi_restore s2
; RV64-ZICFISS-NEXT: addi sp, sp, 32
; RV64-ZICFISS-NEXT: .cfi_def_cfa_offset 0
; RV64-ZICFISS-NEXT: sspopchk ra
; RV64-ZICFISS-NEXT: mop.r.28 zero, ra
; RV64-ZICFISS-NEXT: ret
%res1 = call i32 @bar()
%res2 = call i32 @bar()
Expand Down Expand Up @@ -630,24 +630,24 @@ define i32 @f5_hw() "hw-shadow-stack" nounwind {
;
; RV32-ZICFISS-LABEL: f5_hw:
; RV32-ZICFISS: # %bb.0:
; RV32-ZICFISS-NEXT: sspush ra
; RV32-ZICFISS-NEXT: mop.rr.7 zero, zero, ra
; RV32-ZICFISS-NEXT: addi sp, sp, -16
; RV32-ZICFISS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ZICFISS-NEXT: call bar
; RV32-ZICFISS-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ZICFISS-NEXT: addi sp, sp, 16
; RV32-ZICFISS-NEXT: sspopchk ra
; RV32-ZICFISS-NEXT: mop.r.28 zero, ra
; RV32-ZICFISS-NEXT: ret
;
; RV64-ZICFISS-LABEL: f5_hw:
; RV64-ZICFISS: # %bb.0:
; RV64-ZICFISS-NEXT: sspush ra
; RV64-ZICFISS-NEXT: mop.rr.7 zero, zero, ra
; RV64-ZICFISS-NEXT: addi sp, sp, -16
; RV64-ZICFISS-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-ZICFISS-NEXT: call bar
; RV64-ZICFISS-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-ZICFISS-NEXT: addi sp, sp, 16
; RV64-ZICFISS-NEXT: sspopchk ra
; RV64-ZICFISS-NEXT: mop.r.28 zero, ra
; RV64-ZICFISS-NEXT: ret
%res = call i32 @bar()
%res1 = add i32 %res, 1
Expand Down Expand Up @@ -734,7 +734,7 @@ define i32 @f3_both() "hw-shadow-stack" shadowcallstack {
;
; RV32-ZICFISS-LABEL: f3_both:
; RV32-ZICFISS: # %bb.0:
; RV32-ZICFISS-NEXT: sspush ra
; RV32-ZICFISS-NEXT: mop.rr.7 zero, zero, ra
; RV32-ZICFISS-NEXT: addi sp, sp, -16
; RV32-ZICFISS-NEXT: .cfi_def_cfa_offset 16
; RV32-ZICFISS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
Expand All @@ -744,12 +744,12 @@ define i32 @f3_both() "hw-shadow-stack" shadowcallstack {
; RV32-ZICFISS-NEXT: .cfi_restore ra
; RV32-ZICFISS-NEXT: addi sp, sp, 16
; RV32-ZICFISS-NEXT: .cfi_def_cfa_offset 0
; RV32-ZICFISS-NEXT: sspopchk ra
; RV32-ZICFISS-NEXT: mop.r.28 zero, ra
; RV32-ZICFISS-NEXT: ret
;
; RV64-ZICFISS-LABEL: f3_both:
; RV64-ZICFISS: # %bb.0:
; RV64-ZICFISS-NEXT: sspush ra
; RV64-ZICFISS-NEXT: mop.rr.7 zero, zero, ra
; RV64-ZICFISS-NEXT: addi sp, sp, -16
; RV64-ZICFISS-NEXT: .cfi_def_cfa_offset 16
; RV64-ZICFISS-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
Expand All @@ -759,7 +759,7 @@ define i32 @f3_both() "hw-shadow-stack" shadowcallstack {
; RV64-ZICFISS-NEXT: .cfi_restore ra
; RV64-ZICFISS-NEXT: addi sp, sp, 16
; RV64-ZICFISS-NEXT: .cfi_def_cfa_offset 0
; RV64-ZICFISS-NEXT: sspopchk ra
; RV64-ZICFISS-NEXT: mop.r.28 zero, ra
; RV64-ZICFISS-NEXT: ret
%res = call i32 @bar()
%res1 = add i32 %res, 1
Expand Down Expand Up @@ -849,7 +849,7 @@ define i32 @f4_both() "hw-shadow-stack" shadowcallstack {
;
; RV32-ZICFISS-LABEL: f4_both:
; RV32-ZICFISS: # %bb.0:
; RV32-ZICFISS-NEXT: sspush ra
; RV32-ZICFISS-NEXT: mop.rr.7 zero, zero, ra
; RV32-ZICFISS-NEXT: addi sp, sp, -16
; RV32-ZICFISS-NEXT: .cfi_def_cfa_offset 16
; RV32-ZICFISS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
Expand Down Expand Up @@ -880,12 +880,12 @@ define i32 @f4_both() "hw-shadow-stack" shadowcallstack {
; RV32-ZICFISS-NEXT: .cfi_restore s2
; RV32-ZICFISS-NEXT: addi sp, sp, 16
; RV32-ZICFISS-NEXT: .cfi_def_cfa_offset 0
; RV32-ZICFISS-NEXT: sspopchk ra
; RV32-ZICFISS-NEXT: mop.r.28 zero, ra
; RV32-ZICFISS-NEXT: ret
;
; RV64-ZICFISS-LABEL: f4_both:
; RV64-ZICFISS: # %bb.0:
; RV64-ZICFISS-NEXT: sspush ra
; RV64-ZICFISS-NEXT: mop.rr.7 zero, zero, ra
; RV64-ZICFISS-NEXT: addi sp, sp, -32
; RV64-ZICFISS-NEXT: .cfi_def_cfa_offset 32
; RV64-ZICFISS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
Expand Down Expand Up @@ -916,7 +916,7 @@ define i32 @f4_both() "hw-shadow-stack" shadowcallstack {
; RV64-ZICFISS-NEXT: .cfi_restore s2
; RV64-ZICFISS-NEXT: addi sp, sp, 32
; RV64-ZICFISS-NEXT: .cfi_def_cfa_offset 0
; RV64-ZICFISS-NEXT: sspopchk ra
; RV64-ZICFISS-NEXT: mop.r.28 zero, ra
; RV64-ZICFISS-NEXT: ret
%res1 = call i32 @bar()
%res2 = call i32 @bar()
Expand Down Expand Up @@ -957,24 +957,24 @@ define i32 @f5_both() "hw-shadow-stack" shadowcallstack nounwind {
;
; RV32-ZICFISS-LABEL: f5_both:
; RV32-ZICFISS: # %bb.0:
; RV32-ZICFISS-NEXT: sspush ra
; RV32-ZICFISS-NEXT: mop.rr.7 zero, zero, ra
; RV32-ZICFISS-NEXT: addi sp, sp, -16
; RV32-ZICFISS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ZICFISS-NEXT: call bar
; RV32-ZICFISS-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ZICFISS-NEXT: addi sp, sp, 16
; RV32-ZICFISS-NEXT: sspopchk ra
; RV32-ZICFISS-NEXT: mop.r.28 zero, ra
; RV32-ZICFISS-NEXT: ret
;
; RV64-ZICFISS-LABEL: f5_both:
; RV64-ZICFISS: # %bb.0:
; RV64-ZICFISS-NEXT: sspush ra
; RV64-ZICFISS-NEXT: mop.rr.7 zero, zero, ra
; RV64-ZICFISS-NEXT: addi sp, sp, -16
; RV64-ZICFISS-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-ZICFISS-NEXT: call bar
; RV64-ZICFISS-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-ZICFISS-NEXT: addi sp, sp, 16
; RV64-ZICFISS-NEXT: sspopchk ra
; RV64-ZICFISS-NEXT: mop.r.28 zero, ra
; RV64-ZICFISS-NEXT: ret
%res = call i32 @bar()
%res1 = add i32 %res, 1
Expand Down