[Xtensa] Add esp32/esp8266 cpus implementation. #152409
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Add Xtensa esp32 and esp8266 cpus. Implement target parser to recognise Xtensa hardware features.
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@llvm/pr-subscribers-backend-xtensa Author: Andrei Safronov (andreisfr) ChangesAdd Xtensa esp32 and esp8266 cpus. Implement target parser to recognise Xtensa hardware features. Full diff: https://github.com/llvm/llvm-project/pull/152409.diff 10 Files Affected:
diff --git a/llvm/include/llvm/TargetParser/XtensaTargetParser.def b/llvm/include/llvm/TargetParser/XtensaTargetParser.def
new file mode 100644
index 0000000000000..393721c90d9f3
--- /dev/null
+++ b/llvm/include/llvm/TargetParser/XtensaTargetParser.def
@@ -0,0 +1,79 @@
+//===- XtensaTargetParser.def - Xtensa target parsing defines ---*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides defines to build up the Xtensa target parser's logic.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef XTENSA_FEATURE
+#define XTENSA_FEATURE(ID, STR)
+#endif
+
+XTENSA_FEATURE(FK_DENSITY, "density")
+XTENSA_FEATURE(FK_FP, "fp")
+XTENSA_FEATURE(FK_WINDOWED, "windowed")
+XTENSA_FEATURE(FK_BOOLEAN, "bool")
+XTENSA_FEATURE(FK_LOOP, "loop")
+XTENSA_FEATURE(FK_SEXT, "sext")
+XTENSA_FEATURE(FK_NSA, "nsa")
+XTENSA_FEATURE(FK_CLAMPS, "clamps")
+XTENSA_FEATURE(FK_MINMAX, "minmax")
+XTENSA_FEATURE(FK_MAC16, "mac16")
+XTENSA_FEATURE(FK_MUL32, "mul32")
+XTENSA_FEATURE(FK_MUL32HIGH, "mul32high")
+XTENSA_FEATURE(FK_DIV32, "div32")
+XTENSA_FEATURE(FK_MUL16, "mul16")
+XTENSA_FEATURE(FK_DFPACCEL, "dfpaccel")
+XTENSA_FEATURE(FK_S32C1I, "s32c1i")
+XTENSA_FEATURE(FK_THREADPTR, "threadptr")
+XTENSA_FEATURE(FK_EXTENDEDL32R, "extendedl32r")
+XTENSA_FEATURE(FK_DATACACHE, "dcache")
+XTENSA_FEATURE(FK_DEBUG, "debug")
+XTENSA_FEATURE(FK_EXCEPTION, "exception")
+XTENSA_FEATURE(FK_HIGHPRIINTERRUPTS, "highpriinterrupts")
+XTENSA_FEATURE(FK_HIGHPRIINTERRUPTSLEVEL3, "highpriinterruptslevel3")
+XTENSA_FEATURE(FK_HIGHPRIINTERRUPTSLEVEL4, "highpriinterruptslevel4")
+XTENSA_FEATURE(FK_HIGHPRIINTERRUPTSLEVEL5, "highpriinterruptslevel5")
+XTENSA_FEATURE(FK_HIGHPRIINTERRUPTSLEVEL6, "highpriinterruptslevel6")
+XTENSA_FEATURE(FK_HIGHPRIINTERRUPTSLEVEL7, "highpriinterruptslevel7")
+XTENSA_FEATURE(FK_COPROCESSOR, "coprocessor")
+XTENSA_FEATURE(FK_INTERRUPT, "interrupt")
+XTENSA_FEATURE(FK_RVECTOR, "rvector")
+XTENSA_FEATURE(FK_TIMERS1, "timers1")
+XTENSA_FEATURE(FK_TIMERS2, "timers2")
+XTENSA_FEATURE(FK_TIMERS3, "timers3")
+XTENSA_FEATURE(FK_PRID, "prid")
+XTENSA_FEATURE(FK_REGPROTECT, "regprotect")
+XTENSA_FEATURE(FK_MISCSR, "miscsr")
+
+#undef XTENSA_FEATURE
+
+#ifndef XTENSA_CPU
+#define XTENSA_CPU(ENUM, NAME, FEATURES)
+#endif
+
+XTENSA_CPU(INVALID, {"invalid"}, FK_INVALID)
+XTENSA_CPU(GENERIC, {"generic"}, FK_NONE)
+XTENSA_CPU(ESP8266, {"esp8266"},
+ (FK_DENSITY | FK_NSA | FK_MUL16 | FK_MUL32 | FK_EXTENDEDL32R | FK_DEBUG | FK_EXCEPTION |
+ FK_HIGHPRIINTERRUPTS | FK_HIGHPRIINTERRUPTSLEVEL3 | FK_INTERRUPT | FK_RVECTOR | FK_TIMERS1 |
+ FK_REGPROTECT | FK_PRID))
+XTENSA_CPU(ESP32, {"esp32"},
+ (FK_DENSITY | FK_FP | FK_LOOP | FK_MAC16 | FK_WINDOWED | FK_BOOLEAN | FK_SEXT | FK_NSA |
+ FK_CLAMPS | FK_MINMAX | FK_MUL32 | FK_MUL32HIGH | FK_MUL16 | FK_DFPACCEL | FK_S32C1I |
+ FK_THREADPTR | FK_DIV32 | FK_DATACACHE | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS |
+ FK_HIGHPRIINTERRUPTSLEVEL7 | FK_COPROCESSOR | FK_INTERRUPT | FK_RVECTOR | FK_TIMERS3 | FK_PRID |
+ FK_REGPROTECT | FK_MISCSR))
+
+#undef XTENSA_CPU
+
+#ifndef XTENSA_CPU_ALIAS
+#define XTENSA_CPU_ALIAS(NAME, ALTNMAME)
+#endif
+
+#undef XTENSA_CPU_ALIAS
diff --git a/llvm/include/llvm/TargetParser/XtensaTargetParser.h b/llvm/include/llvm/TargetParser/XtensaTargetParser.h
new file mode 100644
index 0000000000000..3d3ee9971838d
--- /dev/null
+++ b/llvm/include/llvm/TargetParser/XtensaTargetParser.h
@@ -0,0 +1,78 @@
+//==-- XtensaTargetParser - Parser for Xtensa features --*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a target parser to recognise Xtensa hardware features
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TARGETPARSER_XTENSATARGETPARSER_H
+#define LLVM_TARGETPARSER_XTENSATARGETPARSER_H
+
+#include "llvm/TargetParser/Triple.h"
+#include <vector>
+
+namespace llvm {
+class StringRef;
+
+namespace Xtensa {
+
+enum CPUKind : unsigned {
+#define XTENSA_CPU(ENUM, NAME, FEATURES) CK_##ENUM,
+#include "XtensaTargetParser.def"
+};
+
+enum FeatureKind : uint64_t {
+ FK_INVALID = 0,
+ FK_NONE = 1,
+ FK_FP = 1 << 1,
+ FK_WINDOWED = 1 << 2,
+ FK_BOOLEAN = 1 << 3,
+ FK_DENSITY = 1 << 4,
+ FK_LOOP = 1 << 5,
+ FK_SEXT = 1 << 6,
+ FK_NSA = 1 << 7,
+ FK_CLAMPS = 1 << 8,
+ FK_MINMAX = 1 << 9,
+ FK_MAC16 = 1 << 10,
+ FK_MUL32 = 1 << 11,
+ FK_MUL32HIGH = 1 << 12,
+ FK_DIV32 = 1 << 13,
+ FK_MUL16 = 1 << 14,
+ FK_DFPACCEL = 1 << 15,
+ FK_S32C1I = 1 << 16,
+ FK_THREADPTR = 1 << 17,
+ FK_EXTENDEDL32R = 1 << 18,
+ FK_DATACACHE = 1 << 19,
+ FK_DEBUG = 1 << 20,
+ FK_EXCEPTION = 1 << 21,
+ FK_HIGHPRIINTERRUPTS = 1 << 22,
+ FK_HIGHPRIINTERRUPTSLEVEL3 = 1 << 23,
+ FK_HIGHPRIINTERRUPTSLEVEL4 = 1 << 24,
+ FK_HIGHPRIINTERRUPTSLEVEL5 = 1 << 25,
+ FK_HIGHPRIINTERRUPTSLEVEL6 = 1 << 26,
+ FK_HIGHPRIINTERRUPTSLEVEL7 = 1 << 27,
+ FK_COPROCESSOR = 1 << 28,
+ FK_INTERRUPT = 1 << 29,
+ FK_RVECTOR = 1 << 30,
+ FK_TIMERS1 = 1ULL << 31,
+ FK_TIMERS2 = 1ULL << 32,
+ FK_TIMERS3 = 1ULL << 33,
+ FK_PRID = 1ULL << 34,
+ FK_REGPROTECT = 1ULL << 35,
+ FK_MISCSR = 1ULL << 36
+};
+
+CPUKind parseCPUKind(StringRef CPU);
+StringRef getBaseName(StringRef CPU);
+void getCPUFeatures(StringRef CPU, SmallVectorImpl<StringRef> &Features);
+void fillValidCPUList(SmallVectorImpl<StringRef> &Values);
+
+} // namespace Xtensa
+} // namespace llvm
+
+#endif // LLVM_SUPPORT_XTENSATARGETPARSER_H
diff --git a/llvm/include/module.modulemap b/llvm/include/module.modulemap
index ac360b25d7529..98c0c658ca589 100644
--- a/llvm/include/module.modulemap
+++ b/llvm/include/module.modulemap
@@ -415,6 +415,7 @@ module LLVM_Utils {
textual header "llvm/TargetParser/X86TargetParser.def"
textual header "llvm/TargetParser/LoongArchTargetParser.def"
textual header "llvm/TargetParser/PPCTargetParser.def"
+ textual header "llvm/TargetParser/XtensaTargetParser.def"
}
// This part of the module is usable from both C and C++ code.
diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td
index 2c4bacbe8282b..4ef885e19101e 100644
--- a/llvm/lib/Target/Xtensa/Xtensa.td
+++ b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -23,10 +23,8 @@ include "XtensaFeatures.td"
//===----------------------------------------------------------------------===//
// Xtensa supported processors.
//===----------------------------------------------------------------------===//
-class Proc<string Name, list<SubtargetFeature> Features>
- : Processor<Name, NoItineraries, Features>;
-def : Proc<"generic", []>;
+include "XtensaProcessors.td"
//===----------------------------------------------------------------------===//
// Register File Description
diff --git a/llvm/lib/Target/Xtensa/XtensaProcessors.td b/llvm/lib/Target/Xtensa/XtensaProcessors.td
new file mode 100644
index 0000000000000..0faf07d99aaf7
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaProcessors.td
@@ -0,0 +1,27 @@
+//===- XtensaProcessors.td - Xtensa Processors -------------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Xtensa supported processors.
+//===----------------------------------------------------------------------===//
+class Proc<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, NoItineraries, Features>;
+
+def : Proc<"generic", []>;
+
+def : Proc<"esp32", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, FeatureSEXT,
+ FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32,
+ FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureHighPriInterruptsLevel7, FeatureCoprocessor,
+ FeatureInterrupt, FeatureDataCache, FeatureRelocatableVector, FeatureTimers3, FeaturePRID, FeatureRegionProtection, FeatureMiscSR,
+ FeatureMINMAX, FeatureCLAMPS]>;
+
+def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul16, FeatureMul32, FeatureExtendedL32R, FeatureDebug, FeatureException,
+ FeatureHighPriInterrupts, FeatureHighPriInterruptsLevel3, FeatureInterrupt, FeatureRelocatableVector, FeatureTimers1,
+ FeatureRegionProtection, FeaturePRID]>;
diff --git a/llvm/lib/TargetParser/CMakeLists.txt b/llvm/lib/TargetParser/CMakeLists.txt
index 8f8b3a578a1d9..62e97bfebe099 100644
--- a/llvm/lib/TargetParser/CMakeLists.txt
+++ b/llvm/lib/TargetParser/CMakeLists.txt
@@ -27,6 +27,7 @@ add_llvm_component_library(LLVMTargetParser
TargetParser.cpp
Triple.cpp
X86TargetParser.cpp
+ XtensaTargetParser.cpp
ADDITIONAL_HEADER_DIRS
Unix
diff --git a/llvm/lib/TargetParser/XtensaTargetParser.cpp b/llvm/lib/TargetParser/XtensaTargetParser.cpp
new file mode 100644
index 0000000000000..25725f2688cf3
--- /dev/null
+++ b/llvm/lib/TargetParser/XtensaTargetParser.cpp
@@ -0,0 +1,93 @@
+//==-- XtensaTargetParser - Parser for Xtensa features ------------*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a target parser to recognise Xtensa hardware features
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/TargetParser/XtensaTargetParser.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringSwitch.h"
+
+namespace llvm {
+
+namespace Xtensa {
+struct CPUInfo {
+ StringLiteral Name;
+ CPUKind Kind;
+ uint64_t Features;
+};
+
+struct FeatureName {
+ uint64_t ID;
+ const char *NameCStr;
+ size_t NameLength;
+
+ StringRef getName() const { return StringRef(NameCStr, NameLength); }
+};
+
+const FeatureName XtensaFeatureNames[] = {
+#define XTENSA_FEATURE(ID, NAME) {ID, "+" NAME, sizeof(NAME)},
+#include "llvm/TargetParser/XtensaTargetParser.def"
+};
+
+constexpr CPUInfo XtensaCPUInfo[] = {
+#define XTENSA_CPU(ENUM, NAME, FEATURES) {NAME, CK_##ENUM, FEATURES},
+#include "llvm/TargetParser/XtensaTargetParser.def"
+};
+
+StringRef getBaseName(StringRef CPU) {
+ return llvm::StringSwitch<StringRef>(CPU)
+#define XTENSA_CPU_ALIAS(NAME, ANAME) .Case(ANAME, NAME)
+#include "llvm/TargetParser/XtensaTargetParser.def"
+ .Default(CPU);
+}
+
+StringRef getAliasName(StringRef CPU) {
+ return llvm::StringSwitch<StringRef>(CPU)
+#define XTENSA_CPU_ALIAS(NAME, ANAME) .Case(NAME, ANAME)
+#include "llvm/TargetParser/XtensaTargetParser.def"
+ .Default(CPU);
+}
+
+CPUKind parseCPUKind(StringRef CPU) {
+ CPU = getBaseName(CPU);
+ return llvm::StringSwitch<CPUKind>(CPU)
+#define XTENSA_CPU(ENUM, NAME, FEATURES) .Case(NAME, CK_##ENUM)
+#include "llvm/TargetParser/XtensaTargetParser.def"
+ .Default(CK_INVALID);
+}
+
+// Get all features for the CPU
+void getCPUFeatures(StringRef CPU, std::vector<StringRef> &Features) {
+ CPU = getBaseName(CPU);
+ auto I = llvm::find_if(XtensaCPUInfo,
+ [&](const CPUInfo &CI) { return CI.Name == CPU; });
+ assert(I != std::end(XtensaCPUInfo) && "CPU not found!");
+ uint64_t Bits = I->Features;
+
+ for (const auto &F : XtensaFeatureNames) {
+ if ((Bits & F.ID) == F.ID)
+ Features.push_back(F.getName());
+ }
+}
+
+// Find all valid CPUs
+void fillValidCPUList(std::vector<StringRef> &Values) {
+ for (const auto &C : XtensaCPUInfo) {
+ if (C.Kind != CK_INVALID) {
+ Values.emplace_back(C.Name);
+ StringRef Name = getAliasName(C.Name);
+ if (Name != C.Name)
+ Values.emplace_back(Name);
+ }
+ }
+}
+
+} // namespace Xtensa
+} // namespace llvm
diff --git a/llvm/test/CodeGen/Xtensa/cpus-invalid.ll b/llvm/test/CodeGen/Xtensa/cpus-invalid.ll
new file mode 100644
index 0000000000000..d4b51f739e2ab
--- /dev/null
+++ b/llvm/test/CodeGen/Xtensa/cpus-invalid.ll
@@ -0,0 +1,8 @@
+
+; RUN: llc < %s --mtriple=xtensa --mcpu=invalid 2>&1 | FileCheck %s
+
+; CHECK: {{.*}} is not a recognized processor for this target
+
+define void @f() {
+ ret void
+}
diff --git a/llvm/test/CodeGen/Xtensa/cpus.ll b/llvm/test/CodeGen/Xtensa/cpus.ll
new file mode 100644
index 0000000000000..ba2e68695a98c
--- /dev/null
+++ b/llvm/test/CodeGen/Xtensa/cpus.ll
@@ -0,0 +1,12 @@
+; This tests that llc accepts all valid Xtensa CPUs
+
+; RUN: llc < %s --mtriple=xtensa --mcpu=esp8266 2>&1 | FileCheck %s
+; RUN: llc < %s --mtriple=xtensa --mcpu=esp32 2>&1 | FileCheck %s
+; RUN: llc < %s --mtriple=xtensa --mcpu=generic 2>&1 | FileCheck %s
+
+; CHECK-NOT: {{.*}} is not a recognized processor for this target
+; INVALID: {{.*}} is not a recognized processor for this target
+
+define i32 @f(i32 %z) {
+ ret i32 0
+}
diff --git a/llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
index 3dbc803d0d483..183fa57d47a63 100644
--- a/llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
@@ -20,5 +20,6 @@ static_library("TargetParser") {
"TargetParser.cpp",
"Triple.cpp",
"X86TargetParser.cpp",
+ "XtensaTargetParser.cpp",
]
}
|
arsenm
reviewed
Aug 7, 2025
| @@ -0,0 +1,8 @@ | |||
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|||
llvm/test/CodeGen/Xtensa/cpus.ll
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| ; INVALID: {{.*}} is not a recognized processor for this target | ||
|
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||
| define i32 @f(i32 %z) { | ||
| ret i32 0 |
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Suggested change
| ret i32 0 | |
| ret i32 0 |
llvm/test/CodeGen/Xtensa/cpus.ll
Outdated
| ; RUN: llc < %s --mtriple=xtensa --mcpu=generic 2>&1 | FileCheck %s | ||
|
|
||
| ; CHECK-NOT: {{.*}} is not a recognized processor for this target | ||
| ; INVALID: {{.*}} is not a recognized processor for this target |
llvm/test/CodeGen/Xtensa/cpus.ll
Outdated
| ; RUN: llc < %s --mtriple=xtensa --mcpu=esp32 2>&1 | FileCheck %s | ||
| ; RUN: llc < %s --mtriple=xtensa --mcpu=generic 2>&1 | FileCheck %s | ||
|
|
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| ; CHECK-NOT: {{.*}} is not a recognized processor for this target |
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This is too fragile of a not check
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Thank you very much for comments. I changed. test.
MaskRay
approved these changes
Aug 9, 2025
arsenm
approved these changes
Aug 10, 2025
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| define void @f() { | ||
| ret void | ||
| } No newline at end of file |
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Suggested change
| } | |
| } | |
End of file whitespace error
MaskRay
reviewed
Aug 11, 2025
| @@ -0,0 +1,78 @@ | |||
| //==-- XtensaTargetParser - Parser for Xtensa features --*- C++ -*-=// | |||
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https://llvm.org/docs/CodingStandards.html#file-headers
//===----------------------------------------------------------------------===// for new C++ files.
MaskRay
reviewed
Aug 11, 2025
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| enum FeatureKind : uint64_t { | ||
| FK_INVALID = 0, | ||
| FK_NONE = 1, |
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I would avoid FK_NONE which is also a member of enum MCFixupKind.
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ARMTargetParser does use FK_ and a few targets copy it (e.g. LoongArch,CSKY), but I think it's a bad choice. Invent a new prefix for Xtensa FeatureKind?
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Thank you for comment. Fixed.
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/116/builds/16818 Here is the relevant piece of the build log for the reference |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/59/builds/22470 Here is the relevant piece of the build log for the reference |
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Add Xtensa esp32 and esp8266 cpus. Implement target parser to recognise Xtensa hardware features.
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Add Xtensa esp32 and esp8266 cpus. Implement target parser to recognise Xtensa hardware features.