[DAGCombine] Correctly extend the constant RHS in TargetLowering::SimplifySetCC
#152862
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dtcxzyw
requested review from
AlexMaclean,
Artem-B,
RKSimon,
gulfemsavrun,
nikic and
topperc
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@llvm/pr-subscribers-backend-x86 Author: Yingwei Zheng (dtcxzyw) ChangesIn #150270, when the predicate is eq/ne and the trunc has only an nsw flag, the RHS is incorrectly zero-extended. Closes #152630. Full diff: https://github.com/llvm/llvm-project/pull/152862.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index e235d144e85ff..8fbabfa55e93f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5125,10 +5125,11 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
!ISD::isUnsignedIntSetCC(Cond))) &&
isTypeDesirableForOp(ISD::SETCC, N0.getOperand(0).getValueType())) {
EVT NewVT = N0.getOperand(0).getValueType();
- SDValue NewConst = DAG.getConstant(ISD::isSignedIntSetCC(Cond)
- ? C1.sext(NewVT.getSizeInBits())
- : C1.zext(NewVT.getSizeInBits()),
- dl, NewVT);
+ SDValue NewConst = DAG.getConstant(
+ (N0->getFlags().hasNoSignedWrap() && !ISD::isUnsignedIntSetCC(Cond))
+ ? C1.sext(NewVT.getSizeInBits())
+ : C1.zext(NewVT.getSizeInBits()),
+ dl, NewVT);
return DAG.getSetCC(dl, VT, N0.getOperand(0), NewConst, Cond);
}
diff --git a/llvm/test/CodeGen/X86/pr152630.ll b/llvm/test/CodeGen/X86/pr152630.ll
new file mode 100644
index 0000000000000..8fa98831c37b0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr152630.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+
+define i32 @pr152630(i1 %cond) nounwind {
+; CHECK-LABEL: pr152630:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $1, %edi
+; CHECK-NEXT: decl %edi
+; CHECK-NEXT: cmpl $-1, %edi
+; CHECK-NEXT: je .LBB0_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: testl %eax, %eax
+; CHECK-NEXT: jne .LBB0_3
+; CHECK-NEXT: .LBB0_2: # %if.then
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: .LBB0_3: # %if.else
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
+entry:
+ %sel = select i1 %cond, i32 0, i32 -1
+ %conv = trunc nsw i32 %sel to i8
+ switch i8 %conv, label %if.else [
+ i8 -1, label %if.then
+ i8 0, label %if.then
+ ]
+
+if.then:
+ ret i32 0
+
+if.else:
+ ret i32 1
+}
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@llvm/pr-subscribers-llvm-selectiondag Author: Yingwei Zheng (dtcxzyw) ChangesIn #150270, when the predicate is eq/ne and the trunc has only an nsw flag, the RHS is incorrectly zero-extended. Closes #152630. Full diff: https://github.com/llvm/llvm-project/pull/152862.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index e235d144e85ff..8fbabfa55e93f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5125,10 +5125,11 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
!ISD::isUnsignedIntSetCC(Cond))) &&
isTypeDesirableForOp(ISD::SETCC, N0.getOperand(0).getValueType())) {
EVT NewVT = N0.getOperand(0).getValueType();
- SDValue NewConst = DAG.getConstant(ISD::isSignedIntSetCC(Cond)
- ? C1.sext(NewVT.getSizeInBits())
- : C1.zext(NewVT.getSizeInBits()),
- dl, NewVT);
+ SDValue NewConst = DAG.getConstant(
+ (N0->getFlags().hasNoSignedWrap() && !ISD::isUnsignedIntSetCC(Cond))
+ ? C1.sext(NewVT.getSizeInBits())
+ : C1.zext(NewVT.getSizeInBits()),
+ dl, NewVT);
return DAG.getSetCC(dl, VT, N0.getOperand(0), NewConst, Cond);
}
diff --git a/llvm/test/CodeGen/X86/pr152630.ll b/llvm/test/CodeGen/X86/pr152630.ll
new file mode 100644
index 0000000000000..8fa98831c37b0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr152630.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+
+define i32 @pr152630(i1 %cond) nounwind {
+; CHECK-LABEL: pr152630:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $1, %edi
+; CHECK-NEXT: decl %edi
+; CHECK-NEXT: cmpl $-1, %edi
+; CHECK-NEXT: je .LBB0_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: testl %eax, %eax
+; CHECK-NEXT: jne .LBB0_3
+; CHECK-NEXT: .LBB0_2: # %if.then
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: .LBB0_3: # %if.else
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
+entry:
+ %sel = select i1 %cond, i32 0, i32 -1
+ %conv = trunc nsw i32 %sel to i8
+ switch i8 %conv, label %if.else [
+ i8 -1, label %if.then
+ i8 0, label %if.then
+ ]
+
+if.then:
+ ret i32 0
+
+if.else:
+ ret i32 1
+}
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RKSimon
approved these changes
Aug 9, 2025
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/208/builds/3515 Here is the relevant piece of the build log for the reference |
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Heads-up: We saw the following tests used to fail on the original commit under
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@asmok-g Sorry to hear that my change seems to be causing more issues! Would it be possible to attach more details about how to reproduce and whether there is any information produced when clang crashes? I'm very unfamiliar with |
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@AlexMaclean Sorry, I discovered the root-causing of the clang crash was not accurate and I can reproduce it also before this commit. I need a way to test the miscompiles-under-asan caused by the original commit are fixed by this fix. Will update the thread soon. |
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In #150270, when the predicate is eq/ne and the trunc has only an nsw flag, the RHS is incorrectly zero-extended.
Closes #152630.