[AMDGPU] Update GCNHazardRecognizer's understanding of gfx12 waitcount instructions

[rampitec]

This simply updates the pass's cognizance of these instructions, and for the
most part the hazards where they might be encountered do not exist for gfx12.
Nonetheless, encountering them has to be checked for as doing so would indicate
a compiler error.

Co-authored-by: Stephen Thomas [email protected]

[rampitec]

• [AMDGPU] Use encodeFieldVaVdst in hazard recognizer. NFCI. #153881
• [AMDGPU] Update GCNHazardRecognizer's understanding of gfx12 waitcount instructions #153880 👈 (View in Graphite)
• [AMDGPU] w/a for s_setreg_b32 gfx1250 hazard with MODE register #153879
• [AMDGPU] w/a hazard with writing s102/103 and reading FLAT_SCRATCH_BASE #153878
• main

This stack of pull requests is managed by Graphite. Learn more about stacking.

[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Stanislav Mekhanoshin (rampitec)

Changes

This simply updates the pass's cognizance of these instructions, and for the
most part the hazards where they might be encountered do not exist for gfx12.
Nonetheless, encountering them has to be checked for as doing so would indicate
a compiler error.

Co-authored-by: Stephen Thomas <[email protected]>

---

Full diff: https://github.com/llvm/llvm-project/pull/153880.diff

1 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp (+19)

diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index c1cca063aac6f..fa3ca27a5f47c 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1357,6 +1357,16 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
         // DsCnt corresponds to LGKMCnt here.
         return (Decoded.DsCnt == 0);
       }
+      case AMDGPU::S_WAIT_STORECNT:
+      case AMDGPU::S_WAIT_STORECNT_DSCNT:
+      case AMDGPU::S_WAIT_LOADCNT:
+      case AMDGPU::S_WAIT_LOADCNT_DSCNT:
+      case AMDGPU::S_WAIT_SAMPLECNT:
+      case AMDGPU::S_WAIT_BVHCNT:
+      case AMDGPU::S_WAIT_DSCNT:
+      case AMDGPU::S_WAIT_EXPCNT:
+      case AMDGPU::S_WAIT_KMCNT:
+        llvm_unreachable("unexpected wait count instruction");
       default:
         // SOPP instructions cannot mitigate the hazard.
         if (TII->isSOPP(MI))
@@ -2254,6 +2264,15 @@ int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(MachineInstr *MI) {
     case AMDGPU::S_WAITCNT_EXPCNT:
     case AMDGPU::S_WAITCNT_LGKMCNT:
     case AMDGPU::S_WAIT_IDLE:
+    case AMDGPU::S_WAIT_LOADCNT:
+    case AMDGPU::S_WAIT_LOADCNT_DSCNT:
+    case AMDGPU::S_WAIT_SAMPLECNT:
+    case AMDGPU::S_WAIT_BVHCNT:
+    case AMDGPU::S_WAIT_STORECNT:
+    case AMDGPU::S_WAIT_STORECNT_DSCNT:
+    case AMDGPU::S_WAIT_EXPCNT:
+    case AMDGPU::S_WAIT_DSCNT:
+    case AMDGPU::S_WAIT_KMCNT:
       return true;
     default:
       break;

[jayfoad]

I don't really like adding multiple lists of all the waitcnt instructions. #154087 tries to clean this up.