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[AMDGPU] Update GCNHazardRecognizer's understanding of gfx12 waitcount instructions #153880

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Merged
merged 4 commits into from
Aug 16, 2025
Merged

[AMDGPU] Update GCNHazardRecognizer's understanding of gfx12 waitcount instructions #153880

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d9f7d86
[AMDGPU] w/a for s_setreg_b32 gfx1250 hazard with MODE register
rampitec Aug 15, 2025
df0ab0a
[AMDGPU] Update GCNHazardRecognizer's understanding of gfx12 waitcoun…
rampitec Aug 15, 2025
361d496
Merge branch 'main' into users/rampitec/08-15-_amdgpu_update_gcnhazar…
rampitec Aug 15, 2025
30e37b3
Merge branch 'main' into users/rampitec/08-15-_amdgpu_update_gcnhazar…
rampitec Aug 15, 2025
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19 changes: 19 additions & 0 deletions llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1357,6 +1357,16 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
// DsCnt corresponds to LGKMCnt here.
return (Decoded.DsCnt == 0);
}
case AMDGPU::S_WAIT_STORECNT:
case AMDGPU::S_WAIT_STORECNT_DSCNT:
case AMDGPU::S_WAIT_LOADCNT:
case AMDGPU::S_WAIT_LOADCNT_DSCNT:
case AMDGPU::S_WAIT_SAMPLECNT:
case AMDGPU::S_WAIT_BVHCNT:
case AMDGPU::S_WAIT_DSCNT:
case AMDGPU::S_WAIT_EXPCNT:
case AMDGPU::S_WAIT_KMCNT:
llvm_unreachable("unexpected wait count instruction");
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I don't really like adding multiple lists of all the waitcnt instructions. #154087 tries to clean this up.

default:
// SOPP instructions cannot mitigate the hazard.
if (TII->isSOPP(MI))
Expand Down Expand Up @@ -2254,6 +2264,15 @@ int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(MachineInstr *MI) {
case AMDGPU::S_WAITCNT_EXPCNT:
case AMDGPU::S_WAITCNT_LGKMCNT:
case AMDGPU::S_WAIT_IDLE:
case AMDGPU::S_WAIT_LOADCNT:
case AMDGPU::S_WAIT_LOADCNT_DSCNT:
case AMDGPU::S_WAIT_SAMPLECNT:
case AMDGPU::S_WAIT_BVHCNT:
case AMDGPU::S_WAIT_STORECNT:
case AMDGPU::S_WAIT_STORECNT_DSCNT:
case AMDGPU::S_WAIT_EXPCNT:
case AMDGPU::S_WAIT_DSCNT:
case AMDGPU::S_WAIT_KMCNT:
return true;
default:
break;
Expand Down