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2 changes: 1 addition & 1 deletion llvm/lib/Target/Xtensa/XtensaInstrInfo.td
Original file line number Diff line number Diff line change
Expand Up @@ -1407,7 +1407,7 @@ let isBarrier = 1, isTerminator = 1 in {
let r = 0x04;
}

def BREAK_N : RRRN_Inst<0x0C, (outs), (ins uimm4:$imm),
def BREAK_N : RRRN_Inst<0x0D, (outs), (ins uimm4:$imm),
"break.n\t$imm", []>, Requires<[HasDensity, HasDebug]> {
bits<4> imm;

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2 changes: 1 addition & 1 deletion llvm/test/MC/Disassembler/Xtensa/debug.txt
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
# CHECK-DEBUG: break 1, 1
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

[0x2c,0xf1]
[0x2d,0xf1]
# CHECK-DEBUG: break.n 1
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

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2 changes: 1 addition & 1 deletion llvm/test/MC/Xtensa/debug.s
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ break 1, 1

# Instruction format RRRN
# CHECK-INST: break.n 1
# CHECK: encoding: [0x2c,0xf1]
# CHECK: encoding: [0x2d,0xf1]
break.n 1

# Instruction format RRR
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