[AArch64] Fix vectorToScalarBitmask BE (#156312) #156314
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@llvm/pr-subscribers-backend-aarch64 Author: Giuseppe Cesarano (GiuseppeCesarano) ChangesCloses #156312 Full diff: https://github.com/llvm/llvm-project/pull/156314.diff 2 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index b7011e0ea1669..ea83e9d12069b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -24168,6 +24168,7 @@ static SDValue vectorToScalarBitmask(SDNode *N, SelectionDAG &DAG) {
// Ensure that all elements' bits are either 0s or 1s.
ComparisonResult = DAG.getSExtOrTrunc(ComparisonResult, DL, VecVT);
+ bool IsLE = DAG.getDataLayout().isLittleEndian();
SmallVector<SDValue, 16> MaskConstants;
if (DAG.getSubtarget<AArch64Subtarget>().isNeonAvailable() &&
VecVT == MVT::v16i8) {
@@ -24175,7 +24176,10 @@ static SDValue vectorToScalarBitmask(SDNode *N, SelectionDAG &DAG) {
// per entry. We split it into two halves, apply the mask, zip the halves to
// create 8x 16-bit values, and the perform the vector reduce.
for (unsigned Half = 0; Half < 2; ++Half) {
- for (unsigned MaskBit = 1; MaskBit <= 128; MaskBit *= 2) {
+ for (unsigned I = 0; I < 8; ++I) {
+ // On big-endian targets, the lane order in sub-byte vector elements
+ // gets reversed, so we need to flip the bit index.
+ unsigned MaskBit = IsLE ? (1u << I) : (1u << (7 - I));
MaskConstants.push_back(DAG.getConstant(MaskBit, DL, MVT::i32));
}
}
@@ -24193,8 +24197,9 @@ static SDValue vectorToScalarBitmask(SDNode *N, SelectionDAG &DAG) {
}
// All other vector sizes.
- unsigned MaxBitMask = 1u << (VecVT.getVectorNumElements() - 1);
- for (unsigned MaskBit = 1; MaskBit <= MaxBitMask; MaskBit *= 2) {
+ unsigned NumEl = VecVT.getVectorNumElements();
+ for (unsigned I = 0; I < NumEl; ++I) {
+ unsigned MaskBit = IsLE ? (1u << I) : (1u << (NumEl - 1 - I));
MaskConstants.push_back(DAG.getConstant(MaskBit, DL, MVT::i64));
}
diff --git a/llvm/test/CodeGen/AArch64/vector-to-scalar-bitmask.ll b/llvm/test/CodeGen/AArch64/vector-to-scalar-bitmask.ll
new file mode 100644
index 0000000000000..59c8b7389db54
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/vector-to-scalar-bitmask.ll
@@ -0,0 +1,89 @@
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s --check-prefix=CHECK-LE
+; RUN: llc -O0 -mtriple=aarch64_be-linux-gnu %s -o - | FileCheck %s --check-prefix=CHECK-BE
+
+@haystack4 = internal unnamed_addr constant [4 x i32] [i32 0, i32 1, i32 2, i32 3], align 4
+@haystack16 = internal unnamed_addr constant [16 x i8] [i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15], align 16
+
+
+define i8 @test4() {
+ %matches = alloca <4 x i1>, align 1
+ %index_ptr = alloca i64, align 8
+ store i64 0, ptr %index_ptr, align 8
+ %index_val = load i64, ptr %index_ptr, align 8
+ %haystack = getelementptr inbounds i32, ptr getelementptr inbounds (i8, ptr @haystack4, i64 0), i64 %index_val
+ %h_vec = load <4 x i32>, ptr %haystack, align 4
+ %cmp_vec = icmp eq <4 x i32> %h_vec, <i32 2, i32 2, i32 2, i32 2>
+ store <4 x i1> %cmp_vec, ptr %matches, align 1
+ %cmp_load = load <4 x i1>, ptr %matches, align 1
+ %extr = extractelement <4 x i1> %cmp_load, i64 2
+ %ret = zext i1 %extr to i8
+ ret i8 %ret
+}
+
+define i8 @test16() {
+ %matches = alloca <16 x i1>, align 2
+ %index_ptr = alloca i64, align 8
+ store i64 0, ptr %index_ptr, align 8
+ %index_val = load i64, ptr %index_ptr, align 8
+ %haystack = getelementptr inbounds i8, ptr getelementptr inbounds (i8, ptr @haystack16, i64 0), i64 %index_val
+ %h_vec = load <16 x i8>, ptr %haystack, align 16
+ %cmp_vec = icmp eq <16 x i8> %h_vec, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+ store <16 x i1> %cmp_vec, ptr %matches, align 2
+ %cmp_load = load <16 x i1>, ptr %matches, align 2
+ %extr = extractelement <16 x i1> %cmp_load, i64 7
+ %ret = zext i1 %extr to i8
+ ret i8 %ret
+}
+
+; Little endian
+
+; CHECK-LE-LABEL: .LCPI0_0:
+; CHECK-LE-NEXT: .word 1
+; CHECK-LE-NEXT: .word 2
+; CHECK-LE-NEXT: .word 4
+; CHECK-LE-NEXT: .word 8
+
+; CHECK-LE-LABEL: .LCPI1_0:
+; CHECK-LE-NEXT: .byte 1
+; CHECK-LE-NEXT: .byte 2
+; CHECK-LE-NEXT: .byte 4
+; CHECK-LE-NEXT: .byte 8
+; CHECK-LE-NEXT: .byte 16
+; CHECK-LE-NEXT: .byte 32
+; CHECK-LE-NEXT: .byte 64
+; CHECK-LE-NEXT: .byte 128
+; CHECK-LE-NEXT: .byte 1
+; CHECK-LE-NEXT: .byte 2
+; CHECK-LE-NEXT: .byte 4
+; CHECK-LE-NEXT: .byte 8
+; CHECK-LE-NEXT: .byte 16
+; CHECK-LE-NEXT: .byte 32
+; CHECK-LE-NEXT: .byte 64
+; CHECK-LE-NEXT: .byte 128
+
+
+; Big endian
+
+; CHECK-BE-LABEL: .LCPI0_0:
+; CHECK-BE-NEXT: .word 8
+; CHECK-BE-NEXT: .word 4
+; CHECK-BE-NEXT: .word 2
+; CHECK-BE-NEXT: .word 1
+
+; CHECK-BE-LABEL: .LCPI1_0:
+; CHECK-BE-NEXT: .byte 128
+; CHECK-BE-NEXT: .byte 64
+; CHECK-BE-NEXT: .byte 32
+; CHECK-BE-NEXT: .byte 16
+; CHECK-BE-NEXT: .byte 8
+; CHECK-BE-NEXT: .byte 4
+; CHECK-BE-NEXT: .byte 2
+; CHECK-BE-NEXT: .byte 1
+; CHECK-BE-NEXT: .byte 128
+; CHECK-BE-NEXT: .byte 64
+; CHECK-BE-NEXT: .byte 32
+; CHECK-BE-NEXT: .byte 16
+; CHECK-BE-NEXT: .byte 8
+; CHECK-BE-NEXT: .byte 4
+; CHECK-BE-NEXT: .byte 2
+; CHECK-BE-NEXT: .byte 1
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davemgreen
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davemgreen
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Is it possible to add a test that cannot be optimized away and does not require -O0? Or reuse one of the existing ones? This seems difficult to test as the input often includes a bitcast.
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Applying volatile to the vector load and store seems to force the compiler to emit the extraction mask, even at higher levels of optimization. Now, the test doesn't depend on -O0 anymore. Unfortunately, it doesn't seem to be a test that specifically wants to generate this mask, so a completely new one is needed. If other changes are necessary, please let me know. |
Thank that looks a little better, I still worry about the whole global access + compare getting opimized away, and the test just becoming a (volatile) store of a pre-calculated value. I did manage to convince myself that this seems correct for BE. |
I can see what you mean, I've changed the test as you suggested basically coping and pasting the functions which you pointed out. The only issue is that I would like to avoid using It may even prompt the user to rerun |
I see what you mean, but often they can be intertwined and if the codegen changes the lane masks should be changed to accommodate. Lets go with this version and we can always add extra lines in the future if needed. |
davemgreen
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LGTM, thanks for the fix.
Are you happy for me to to hit submit?
I see your point. I think both versions have their own issues. The current version relies on the correspondence between bits and lanes: This correspondence holds today, but it is not explicitly checked. I’ve seen other issues caused by this endianness differences, and in those cases the problem was fixed in the surrounding logic and not in the bit–lane mapping itself. For that reason I think this correspondence is unlikely to change, or at least such patch would require special care if it ever did. If you have a suggestion for how to assert or verify this mapping, I’ll be happy to add it. Otherwise, I’m fine with the patch being merged as is. |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/24/builds/12373 Here is the relevant piece of the build log for the reference |
The error seems to be unrelated with this patch, it occurs in linking for x86 targets while the current patch only changes aarch64_be codegen |
4 participants
Closes #156312