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[AArch64] Fix vectorToScalarBitmask BE (#156312) #156314

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Merged
merged 3 commits into from
Sep 7, 2025
Merged

[AArch64] Fix vectorToScalarBitmask BE (#156312) #156314

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d294d46
[AArch64] Fix vectorToScalarBitmask BE (#156312)
GiuseppeCesarano Sep 1, 2025
1fd14af
Made test not require -O0
GiuseppeCesarano Sep 3, 2025
e4dbcae
Removed compile time known constants from the test
GiuseppeCesarano Sep 4, 2025
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11 changes: 8 additions & 3 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -24168,14 +24168,18 @@ static SDValue vectorToScalarBitmask(SDNode *N, SelectionDAG &DAG) {
// Ensure that all elements' bits are either 0s or 1s.
ComparisonResult = DAG.getSExtOrTrunc(ComparisonResult, DL, VecVT);

bool IsLE = DAG.getDataLayout().isLittleEndian();
SmallVector<SDValue, 16> MaskConstants;
if (DAG.getSubtarget<AArch64Subtarget>().isNeonAvailable() &&
VecVT == MVT::v16i8) {
// v16i8 is a special case, as we have 16 entries but only 8 positional bits
// per entry. We split it into two halves, apply the mask, zip the halves to
// create 8x 16-bit values, and the perform the vector reduce.
for (unsigned Half = 0; Half < 2; ++Half) {
for (unsigned MaskBit = 1; MaskBit <= 128; MaskBit *= 2) {
for (unsigned I = 0; I < 8; ++I) {
// On big-endian targets, the lane order in sub-byte vector elements
// gets reversed, so we need to flip the bit index.
unsigned MaskBit = IsLE ? (1u << I) : (1u << (7 - I));
MaskConstants.push_back(DAG.getConstant(MaskBit, DL, MVT::i32));
}
}
Expand All @@ -24193,8 +24197,9 @@ static SDValue vectorToScalarBitmask(SDNode *N, SelectionDAG &DAG) {
}

// All other vector sizes.
unsigned MaxBitMask = 1u << (VecVT.getVectorNumElements() - 1);
for (unsigned MaskBit = 1; MaskBit <= MaxBitMask; MaskBit *= 2) {
unsigned NumEl = VecVT.getVectorNumElements();
for (unsigned I = 0; I < NumEl; ++I) {
unsigned MaskBit = IsLE ? (1u << I) : (1u << (NumEl - 1 - I));
MaskConstants.push_back(DAG.getConstant(MaskBit, DL, MVT::i64));
}

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89 changes: 89 additions & 0 deletions llvm/test/CodeGen/AArch64/vector-to-scalar-bitmask.ll
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@@ -0,0 +1,89 @@
; RUN: llc -O0 -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s --check-prefix=CHECK-LE
; RUN: llc -O0 -mtriple=aarch64_be-linux-gnu %s -o - | FileCheck %s --check-prefix=CHECK-BE

@haystack4 = internal unnamed_addr constant [4 x i32] [i32 0, i32 1, i32 2, i32 3], align 4
@haystack16 = internal unnamed_addr constant [16 x i8] [i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15], align 16


define i8 @test4() {
%matches = alloca <4 x i1>, align 1
%index_ptr = alloca i64, align 8
store i64 0, ptr %index_ptr, align 8
%index_val = load i64, ptr %index_ptr, align 8
%haystack = getelementptr inbounds i32, ptr getelementptr inbounds (i8, ptr @haystack4, i64 0), i64 %index_val
%h_vec = load <4 x i32>, ptr %haystack, align 4
%cmp_vec = icmp eq <4 x i32> %h_vec, <i32 2, i32 2, i32 2, i32 2>
store <4 x i1> %cmp_vec, ptr %matches, align 1
%cmp_load = load <4 x i1>, ptr %matches, align 1
%extr = extractelement <4 x i1> %cmp_load, i64 2
%ret = zext i1 %extr to i8
ret i8 %ret
}

define i8 @test16() {
%matches = alloca <16 x i1>, align 2
%index_ptr = alloca i64, align 8
store i64 0, ptr %index_ptr, align 8
%index_val = load i64, ptr %index_ptr, align 8
%haystack = getelementptr inbounds i8, ptr getelementptr inbounds (i8, ptr @haystack16, i64 0), i64 %index_val
%h_vec = load <16 x i8>, ptr %haystack, align 16
%cmp_vec = icmp eq <16 x i8> %h_vec, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
store <16 x i1> %cmp_vec, ptr %matches, align 2
%cmp_load = load <16 x i1>, ptr %matches, align 2
%extr = extractelement <16 x i1> %cmp_load, i64 7
%ret = zext i1 %extr to i8
ret i8 %ret
}

; Little endian

; CHECK-LE-LABEL: .LCPI0_0:
; CHECK-LE-NEXT: .word 1
; CHECK-LE-NEXT: .word 2
; CHECK-LE-NEXT: .word 4
; CHECK-LE-NEXT: .word 8

; CHECK-LE-LABEL: .LCPI1_0:
; CHECK-LE-NEXT: .byte 1
; CHECK-LE-NEXT: .byte 2
; CHECK-LE-NEXT: .byte 4
; CHECK-LE-NEXT: .byte 8
; CHECK-LE-NEXT: .byte 16
; CHECK-LE-NEXT: .byte 32
; CHECK-LE-NEXT: .byte 64
; CHECK-LE-NEXT: .byte 128
; CHECK-LE-NEXT: .byte 1
; CHECK-LE-NEXT: .byte 2
; CHECK-LE-NEXT: .byte 4
; CHECK-LE-NEXT: .byte 8
; CHECK-LE-NEXT: .byte 16
; CHECK-LE-NEXT: .byte 32
; CHECK-LE-NEXT: .byte 64
; CHECK-LE-NEXT: .byte 128


; Big endian

; CHECK-BE-LABEL: .LCPI0_0:
; CHECK-BE-NEXT: .word 8
; CHECK-BE-NEXT: .word 4
; CHECK-BE-NEXT: .word 2
; CHECK-BE-NEXT: .word 1

; CHECK-BE-LABEL: .LCPI1_0:
; CHECK-BE-NEXT: .byte 128
; CHECK-BE-NEXT: .byte 64
; CHECK-BE-NEXT: .byte 32
; CHECK-BE-NEXT: .byte 16
; CHECK-BE-NEXT: .byte 8
; CHECK-BE-NEXT: .byte 4
; CHECK-BE-NEXT: .byte 2
; CHECK-BE-NEXT: .byte 1
; CHECK-BE-NEXT: .byte 128
; CHECK-BE-NEXT: .byte 64
; CHECK-BE-NEXT: .byte 32
; CHECK-BE-NEXT: .byte 16
; CHECK-BE-NEXT: .byte 8
; CHECK-BE-NEXT: .byte 4
; CHECK-BE-NEXT: .byte 2
; CHECK-BE-NEXT: .byte 1