[X86][LiveRegUnits] Exclude reserved registers from TargetRegisterClass

[phoebewang]

Fixes regression casued by #156817.

[llvmbot]

@llvm/pr-subscribers-backend-x86

Author: Phoebe Wang (phoebewang)

Changes

Fixes regression casued by #156817.

---

Full diff: https://github.com/llvm/llvm-project/pull/157798.diff

2 Files Affected:

• (modified) llvm/lib/Target/X86/X86RegisterInfo.cpp (+2-1)
• (added) llvm/test/CodeGen/X86/pr156817.ll (+23)

diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 5b365f8cb1449..edba313c25df8 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -999,6 +999,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 unsigned X86RegisterInfo::findDeadCallerSavedReg(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const {
   const MachineFunction *MF = MBB.getParent();
+  const MachineRegisterInfo &MRI = MF->getRegInfo();
   if (MF->callsEHReturn())
     return 0;
 
@@ -1030,7 +1031,7 @@ unsigned X86RegisterInfo::findDeadCallerSavedReg(
     const TargetRegisterClass &RC =
         Is64Bit ? X86::GR64_NOSPRegClass : X86::GR32_NOSPRegClass;
     for (MCRegister Reg : RC) {
-      if (LRU.available(Reg))
+      if (LRU.available(Reg) && !MRI.isReserved(Reg))
         return Reg;
     }
   }
diff --git a/llvm/test/CodeGen/X86/pr156817.ll b/llvm/test/CodeGen/X86/pr156817.ll
new file mode 100644
index 0000000000000..80972ecc5abb5
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr156817.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64 -mattr=+egpr | FileCheck %s --check-prefix=EGPR
+
+define coldcc i32 @foo() nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    callq bar@PLT
+; CHECK-NEXT:    addq $8, %rsp
+; CHECK-NEXT:    retq
+;
+; EGPR-LABEL: foo:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    pushq %rax
+; EGPR-NEXT:    callq bar@PLT
+; EGPR-NEXT:    popq %r16
+; EGPR-NEXT:    retq
+  %1 = tail call coldcc i32 @bar()
+  ret i32 %1
+}
+
+declare coldcc i32 @bar()