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[X86][LiveRegUnits] Exclude reserved registers from TargetRegisterClass #157798

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Merged
phoebewang merged 1 commit into from
Sep 10, 2025
Merged

[X86][LiveRegUnits] Exclude reserved registers from TargetRegisterClass #157798

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3 changes: 2 additions & 1 deletion llvm/lib/Target/X86/X86RegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -999,6 +999,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
unsigned X86RegisterInfo::findDeadCallerSavedReg(
MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const {
const MachineFunction *MF = MBB.getParent();
const MachineRegisterInfo &MRI = MF->getRegInfo();
if (MF->callsEHReturn())
return 0;

Expand Down Expand Up @@ -1030,7 +1031,7 @@ unsigned X86RegisterInfo::findDeadCallerSavedReg(
const TargetRegisterClass &RC =
Is64Bit ? X86::GR64_NOSPRegClass : X86::GR32_NOSPRegClass;
for (MCRegister Reg : RC) {
if (LRU.available(Reg))
if (LRU.available(Reg) && !MRI.isReserved(Reg))
return Reg;
}
}
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23 changes: 23 additions & 0 deletions llvm/test/CodeGen/X86/pr156817.ll
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@@ -0,0 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64 -mattr=+egpr | FileCheck %s --check-prefix=EGPR

define coldcc i32 @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq bar@PLT
; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: retq
;
; EGPR-LABEL: foo:
; EGPR: # %bb.0:
; EGPR-NEXT: pushq %rax
; EGPR-NEXT: callq bar@PLT
; EGPR-NEXT: popq %r16
; EGPR-NEXT: retq
%1 = tail call coldcc i32 @bar()
ret i32 %1
}

declare coldcc i32 @bar()