X86: Elide use of RegClassByHwMode in some ptr_rc_tailcall uses

[arsenm]

Different instructions are used for the 32-bit and 64-bit cases
anyway, so directly use the concrete register class in the
instruction.

[arsenm]

• X86: Elide use of RegClassByHwMode in some ptr_rc_tailcall uses #159874 👈 (View in Graphite)
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[llvmbot]

@llvm/pr-subscribers-backend-x86

Author: Matt Arsenault (arsenm)

Changes

Different instructions are used for the 32-bit and 64-bit cases
anyway, so directly use the concrete register class in the
instruction.

---

Full diff: https://github.com/llvm/llvm-project/pull/159874.diff

2 Files Affected:

• (modified) llvm/lib/Target/X86/X86InstrCompiler.td (+2-2)
• (modified) llvm/lib/Target/X86/X86InstrControl.td (+2-2)

diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index af7a33abaf758..0fd44b74fd449 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -1324,8 +1324,8 @@ def : Pat<(X86imp_call (i64 tglobaladdr:$dst)),
 // %r11. This happens when calling a vararg function with 6 arguments.
 //
 // Match an X86tcret that uses less than 7 volatile registers.
-def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off),
-          (TCRETURNri ptr_rc_tailcall:$dst, timm:$off)>,
+def : Pat<(X86tcret GR32_TC:$dst, timm:$off),
+          (TCRETURNri GR32_TC:$dst, timm:$off)>,
           Requires<[Not64BitMode, IsNotHiPECCFunc, NotUseIndirectThunkCalls]>;
 
 def : Pat<(X86tcret GR32:$dst, timm:$off),
diff --git a/llvm/lib/Target/X86/X86InstrControl.td b/llvm/lib/Target/X86/X86InstrControl.td
index d962bfff1444d..e8527cd73abb5 100644
--- a/llvm/lib/Target/X86/X86InstrControl.td
+++ b/llvm/lib/Target/X86/X86InstrControl.td
@@ -280,7 +280,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
     isCodeGenOnly = 1, Uses = [ESP, SSP] in {
   def TCRETURNdi : PseudoI<(outs), (ins i32imm_brtarget:$dst, i32imm:$offset),
                            []>, Sched<[WriteJump]>;
-  def TCRETURNri : PseudoI<(outs), (ins ptr_rc_tailcall:$dst, i32imm:$offset),
+  def TCRETURNri : PseudoI<(outs), (ins GR32_TC:$dst, i32imm:$offset),
                            []>, Sched<[WriteJump]>;
 
   def TCRETURN_HIPE32ri : PseudoI<(outs), (ins GR32:$dst, i32imm:$offset),
@@ -359,7 +359,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
                                (ins i64i32imm_brtarget:$dst, i32imm:$offset),
                                []>, Sched<[WriteJump]>;
   def TCRETURNri64   : PseudoI<(outs),
-                               (ins ptr_rc_tailcall:$dst, i32imm:$offset),
+                               (ins GR64_TC:$dst, i32imm:$offset),
                                []>, Sched<[WriteJump]>;
   def TCRETURN_WIN64ri : PseudoI<(outs), (ins GR64_TCW64:$dst, i32imm:$offset),
                                 []>, Sched<[WriteJump]>;

[topperc]

Not blocking for this patch, but should this be called TCRETURNri32 to make this more clear?

[arsenm]

Probably

[topperc]

LGTM