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X86: Elide use of RegClassByHwMode in some ptr_rc_tailcall uses #159874

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Merged
merged 1 commit into from
Sep 20, 2025
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X86: Elide use of RegClassByHwMode in some ptr_rc_tailcall uses #159874

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4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86InstrCompiler.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1324,8 +1324,8 @@ def : Pat<(X86imp_call (i64 tglobaladdr:$dst)),
// %r11. This happens when calling a vararg function with 6 arguments.
//
// Match an X86tcret that uses less than 7 volatile registers.
def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off),
(TCRETURNri ptr_rc_tailcall:$dst, timm:$off)>,
def : Pat<(X86tcret GR32_TC:$dst, timm:$off),
(TCRETURNri GR32_TC:$dst, timm:$off)>,
Requires<[Not64BitMode, IsNotHiPECCFunc, NotUseIndirectThunkCalls]>;

def : Pat<(X86tcret GR32:$dst, timm:$off),
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4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86InstrControl.td
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Expand Up @@ -280,7 +280,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
isCodeGenOnly = 1, Uses = [ESP, SSP] in {
def TCRETURNdi : PseudoI<(outs), (ins i32imm_brtarget:$dst, i32imm:$offset),
[]>, Sched<[WriteJump]>;
def TCRETURNri : PseudoI<(outs), (ins ptr_rc_tailcall:$dst, i32imm:$offset),
def TCRETURNri : PseudoI<(outs), (ins GR32_TC:$dst, i32imm:$offset),
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@topperc topperc Sep 19, 2025

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Not blocking for this patch, but should this be called TCRETURNri32 to make this more clear?

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@arsenm arsenm Sep 20, 2025

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Probably

[]>, Sched<[WriteJump]>;

def TCRETURN_HIPE32ri : PseudoI<(outs), (ins GR32:$dst, i32imm:$offset),
Expand Down Expand Up @@ -359,7 +359,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
(ins i64i32imm_brtarget:$dst, i32imm:$offset),
[]>, Sched<[WriteJump]>;
def TCRETURNri64 : PseudoI<(outs),
(ins ptr_rc_tailcall:$dst, i32imm:$offset),
(ins GR64_TC:$dst, i32imm:$offset),
[]>, Sched<[WriteJump]>;
def TCRETURN_WIN64ri : PseudoI<(outs), (ins GR64_TCW64:$dst, i32imm:$offset),
[]>, Sched<[WriteJump]>;
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