[TargetLowering][ARM][PowerPC] LHS and RHS should be frozen for 3-way compares

[AZero13]

LHS and RHS are used multiple times.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-backend-systemz
@llvm/pr-subscribers-backend-powerpc
@llvm/pr-subscribers-backend-x86
@llvm/pr-subscribers-llvm-globalisel
@llvm/pr-subscribers-llvm-selectiondag

@llvm/pr-subscribers-backend-arm

Author: AZero13 (AZero13)

Changes

LHS and RHS are used multiple times.

---

Full diff: https://github.com/llvm/llvm-project/pull/159993.diff

1 Files Affected:

• (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+3)

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 9052cbfa89deb..9905a4457f35b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -10479,6 +10479,9 @@ SDValue ARMTargetLowering::LowerCMP(SDValue Op, SelectionDAG &DAG) const {
 
   // Special case for Thumb1 UCMP only
   if (!IsSigned && Subtarget->isThumb1Only()) {
+    LHS = DAG.getFreeze(LHS);
+    RHS = DAG.getFreeze(RHS);
+
     // For Thumb unsigned comparison, use this sequence:
     // subs r2, r0, r1   ; r2 = LHS - RHS, sets flags
     // sbc r2, r2        ; r2 = r2 - r2 - !carry

[arsenm]

Missing tests

[arsenm]

Alive doesn't seem to think this is necessary: https://alive2.llvm.org/ce/z/JLx9Rb

[AZero13]

Alive doesn't seem to think this is necessary: https://alive2.llvm.org/ce/z/JLx9Rb

Wonder if I should remove it from the PowerPC ucmp then if true...

I'll look into this tomorrow