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[TargetLowering][ARM][PowerPC] LHS and RHS should be frozen for 3-way compares #159993

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[TargetLowering][ARM][PowerPC] LHS and RHS should be frozen for 3-way compares #159993

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dd52fba
[TargetLowering] Freeze operands in UCMP and SCMP
AZero13 Sep 21, 2025
cabcd82
Fix mitigiations in PowerPC by having custom lowering anyway
AZero13 Sep 22, 2025
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8 changes: 4 additions & 4 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Expand Up @@ -8582,6 +8582,8 @@ LegalizerHelper::lowerThreewayCompare(MachineInstr &MI) {
LLT DstTy = MRI.getType(Dst);
LLT SrcTy = MRI.getType(Cmp->getReg(1));
LLT CmpTy = DstTy.changeElementSize(1);
auto LHS = MIRBuilder.buildFreeze(SrcTy, Cmp->getLHSReg());
auto RHS = MIRBuilder.buildFreeze(SrcTy, Cmp->getRHSReg());

CmpInst::Predicate LTPredicate = Cmp->isSigned()
? CmpInst::Predicate::ICMP_SLT
Expand All @@ -8591,10 +8593,8 @@ LegalizerHelper::lowerThreewayCompare(MachineInstr &MI) {
: CmpInst::Predicate::ICMP_UGT;

auto Zero = MIRBuilder.buildConstant(DstTy, 0);
auto IsGT = MIRBuilder.buildICmp(GTPredicate, CmpTy, Cmp->getLHSReg(),
Cmp->getRHSReg());
auto IsLT = MIRBuilder.buildICmp(LTPredicate, CmpTy, Cmp->getLHSReg(),
Cmp->getRHSReg());
auto IsGT = MIRBuilder.buildICmp(GTPredicate, CmpTy, LHS, RHS);
auto IsLT = MIRBuilder.buildICmp(LTPredicate, CmpTy, LHS, RHS);

auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
auto BC = TLI.getBooleanContents(DstTy.isVector(), /*isFP=*/false);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Expand Up @@ -10956,8 +10956,8 @@ SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {

SDValue TargetLowering::expandCMP(SDNode *Node, SelectionDAG &DAG) const {
unsigned Opcode = Node->getOpcode();
SDValue LHS = Node->getOperand(0);
SDValue RHS = Node->getOperand(1);
SDValue LHS = DAG.getFreeze(Node->getOperand(0));
SDValue RHS = DAG.getFreeze(Node->getOperand(1));
EVT VT = LHS.getValueType();
EVT ResVT = Node->getValueType(0);
EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
Expand Down
13 changes: 5 additions & 8 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Expand Up @@ -10479,6 +10479,9 @@ SDValue ARMTargetLowering::LowerCMP(SDValue Op, SelectionDAG &DAG) const {

// Special case for Thumb1 UCMP only
if (!IsSigned && Subtarget->isThumb1Only()) {
LHS = DAG.getFreeze(LHS);
RHS = DAG.getFreeze(RHS);

// For Thumb unsigned comparison, use this sequence:
// subs r2, r0, r1 ; r2 = LHS - RHS, sets flags
// sbc r2, r2 ; r2 = r2 - r2 - !carry
Expand Down Expand Up @@ -10511,10 +10514,7 @@ SDValue ARMTargetLowering::LowerCMP(SDValue Op, SelectionDAG &DAG) const {
// Final subtraction: Sbc1Result - Sbc2Result (no flags needed)
SDValue Result =
DAG.getNode(ISD::SUB, dl, MVT::i32, Sbc1Result, Sbc2Result);
if (Op.getValueType() != MVT::i32)
Result = DAG.getSExtOrTrunc(Result, dl, Op.getValueType());

return Result;
return DAG.getSExtOrTrunc(Result, dl, Op.getValueType());
}

// For the ARM assembly pattern:
Expand Down Expand Up @@ -10582,10 +10582,7 @@ SDValue ARMTargetLowering::LowerCMP(SDValue Op, SelectionDAG &DAG) const {
SDValue Result2 = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, Result1, MinusOne,
LTCondValue, Flags);

if (Op.getValueType() != MVT::i32)
Result2 = DAG.getSExtOrTrunc(Result2, dl, Op.getValueType());

return Result2;
return DAG.getSExtOrTrunc(Result2, dl, Op.getValueType());
}

SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
Expand Down
33 changes: 33 additions & 0 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Expand Up @@ -585,6 +585,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);

// Custom handling for PowerPC ucmp instruction
setOperationAction(ISD::UCMP, MVT::i32, Custom);
setOperationAction(ISD::UCMP, MVT::i64, isPPC64 ? Custom : Expand);

// NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
// SjLj exception handling but a light-weight setjmp/longjmp replacement to
// support continuation, user-level threading, and etc.. As a result, no
Expand Down Expand Up @@ -12618,6 +12622,33 @@ SDValue PPCTargetLowering::LowerSSUBO(SDValue Op, SelectionDAG &DAG) const {
return DAG.getMergeValues({Sub, OverflowTrunc}, dl);
}

// Lower unsigned 3-way compare producing -1/0/1.
SDValue PPCTargetLowering::LowerUCMP(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);
SDValue A = DAG.getFreeze(Op.getOperand(0));
SDValue B = DAG.getFreeze(Op.getOperand(1));
EVT OpVT = A.getValueType(); // operand type
EVT ResVT = Op.getValueType(); // result type

// First compute diff = A - B (will become subf).
SDValue Diff = DAG.getNode(ISD::SUB, DL, OpVT, A, B);

// Generate B - A using SUBC to capture carry.
SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
SDValue SubC = DAG.getNode(PPCISD::SUBC, DL, VTs, B, A);
SDValue CA0 = SubC.getValue(1);

// t2 = A - B + CA0 using SUBE.
SDValue SubE1 = DAG.getNode(PPCISD::SUBE, DL, VTs, A, B, CA0);
SDValue CA1 = SubE1.getValue(1);

// res = diff - t2 + CA1 using SUBE (produces desired -1/0/1).
SDValue ResPair = DAG.getNode(PPCISD::SUBE, DL, VTs, Diff, SubE1, CA1);

// Extract the first result and truncate to result type if needed
return DAG.getSExtOrTrunc(ResPair.getValue(0), DL, ResVT);
}

/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
Expand Down Expand Up @@ -12722,6 +12753,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::UADDO_CARRY:
case ISD::USUBO_CARRY:
return LowerADDSUBO_CARRY(Op, DAG);
case ISD::UCMP:
return LowerUCMP(Op, DAG);
}
}

Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/PowerPC/PPCISelLowering.h
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Expand Up @@ -1343,6 +1343,7 @@ namespace llvm {
SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUCMP(SDValue Op, SelectionDAG &DAG) const;

SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
Expand Down
34 changes: 22 additions & 12 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-threeway-cmp.mir
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Expand Up @@ -7,8 +7,10 @@ body: |
; CHECK-LABEL: name: test_scmp
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY]]
; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(s64) = G_FREEZE [[COPY1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[FREEZE]](s64), [[FREEZE1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[FREEZE]](s64), [[FREEZE1]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C]], [[C1]]
Expand All @@ -30,8 +32,10 @@ body: |
; CHECK-LABEL: name: test_ucmp
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY]]
; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(s64) = G_FREEZE [[COPY1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[FREEZE]](s64), [[FREEZE1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[FREEZE]](s64), [[FREEZE1]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C]], [[C1]]
Expand Down Expand Up @@ -61,8 +65,10 @@ body: |
; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $w3
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ugt), [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ult), [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]]
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x s32>) = G_FREEZE [[BUILD_VECTOR]]
; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(<4 x s32>) = G_FREEZE [[BUILD_VECTOR1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ugt), [[FREEZE]](<4 x s32>), [[FREEZE1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ult), [[FREEZE]](<4 x s32>), [[FREEZE1]]
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s16>) = G_SUB [[TRUNC]], [[TRUNC1]]
Expand Down Expand Up @@ -92,13 +98,17 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[DEF]](s64), [[DEF]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[DEF]]
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY]]
; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(s64) = G_FREEZE [[DEF]]
; CHECK-NEXT: [[FREEZE2:%[0-9]+]]:_(s64) = G_FREEZE [[COPY1]]
; CHECK-NEXT: [[FREEZE3:%[0-9]+]]:_(s64) = G_FREEZE [[DEF]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[FREEZE]](s64), [[FREEZE2]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[FREEZE1]](s64), [[FREEZE3]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[FREEZE1]](s64), [[FREEZE3]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[DEF]]
; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[DEF]]
; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[FREEZE]](s64), [[FREEZE2]]
; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[FREEZE1]](s64), [[FREEZE3]]
; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[FREEZE1]](s64), [[FREEZE3]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), [[ICMP3]], [[ICMP4]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
Expand Down
32 changes: 22 additions & 10 deletions llvm/test/CodeGen/AArch64/freeze.ll
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Expand Up @@ -522,16 +522,28 @@ define i32 @freeze_scmp(i32 %a0) nounwind {
}

define i32 @freeze_ucmp(i32 %a0) nounwind {
; CHECK-LABEL: freeze_ucmp:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #2 // =0x2
; CHECK-NEXT: cmp w8, w0
; CHECK-NEXT: cset w8, hi
; CHECK-NEXT: csinv w8, w8, wzr, hs
; CHECK-NEXT: cmp w8, #1
; CHECK-NEXT: cset w8, hi
; CHECK-NEXT: csinv w0, w8, wzr, hs
; CHECK-NEXT: ret
; CHECK-SD-LABEL: freeze_ucmp:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov w8, #2 // =0x2
; CHECK-SD-NEXT: cmp w8, w0
; CHECK-SD-NEXT: cset w8, hi
; CHECK-SD-NEXT: csinv w8, w8, wzr, hs
; CHECK-SD-NEXT: cmp w8, #1
; CHECK-SD-NEXT: cset w8, hi
; CHECK-SD-NEXT: csinv w0, w8, wzr, hs
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: freeze_ucmp:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #2 // =0x2
; CHECK-GI-NEXT: mov w9, #1 // =0x1
; CHECK-GI-NEXT: cmp w8, w0
; CHECK-GI-NEXT: cset w8, hi
; CHECK-GI-NEXT: csinv w8, w8, wzr, hs
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: cset w8, hi
; CHECK-GI-NEXT: csinv w0, w8, wzr, hs
; CHECK-GI-NEXT: ret
%x = call i32 @llvm.ucmp.i32(i32 2, i32 %a0)
%y = freeze i32 %x
%z = call i32 @llvm.ucmp.i32(i32 %y, i32 1)
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/ucmp.ll
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Expand Up @@ -13,8 +13,8 @@ define i8 @ucmp.8.8(i8 %x, i8 %y) nounwind {
;
; CHECK-GI-LABEL: ucmp.8.8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: and w8, w0, #0xff
; CHECK-GI-NEXT: and w9, w1, #0xff
; CHECK-GI-NEXT: uxtb w8, w0
; CHECK-GI-NEXT: uxtb w9, w1
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: cset w8, hi
; CHECK-GI-NEXT: csinv w0, w8, wzr, hs
Expand All @@ -34,8 +34,8 @@ define i8 @ucmp.8.16(i16 %x, i16 %y) nounwind {
;
; CHECK-GI-LABEL: ucmp.8.16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: and w8, w0, #0xffff
; CHECK-GI-NEXT: and w9, w1, #0xffff
; CHECK-GI-NEXT: uxth w8, w0
; CHECK-GI-NEXT: uxth w9, w1
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: cset w8, hi
; CHECK-GI-NEXT: csinv w0, w8, wzr, hs
Expand Down
30 changes: 15 additions & 15 deletions llvm/test/CodeGen/ARM/scmp.ll
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Expand Up @@ -58,23 +58,23 @@ define i8 @scmp_8_128(i128 %x, i128 %y) nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: ldr r4, [sp, #24]
; CHECK-NEXT: mov r5, #0
; CHECK-NEXT: ldr r6, [sp, #28]
; CHECK-NEXT: subs r7, r0, r4
; CHECK-NEXT: ldr r12, [sp, #32]
; CHECK-NEXT: sbcs r7, r1, r6
; CHECK-NEXT: ldr lr, [sp, #36]
; CHECK-NEXT: sbcs r7, r2, r12
; CHECK-NEXT: sbcs r7, r3, lr
; CHECK-NEXT: ldr r5, [sp, #24]
; CHECK-NEXT: mov r6, #0
; CHECK-NEXT: ldr r4, [sp, #28]
; CHECK-NEXT: subs r7, r0, r5
; CHECK-NEXT: ldr lr, [sp, #32]
; CHECK-NEXT: sbcs r7, r1, r4
; CHECK-NEXT: ldr r12, [sp, #36]
; CHECK-NEXT: sbcs r7, r2, lr
; CHECK-NEXT: sbcs r7, r3, r12
; CHECK-NEXT: mov r7, #0
; CHECK-NEXT: movwlt r7, #1
; CHECK-NEXT: subs r0, r4, r0
; CHECK-NEXT: sbcs r0, r6, r1
; CHECK-NEXT: sbcs r0, r12, r2
; CHECK-NEXT: sbcs r0, lr, r3
; CHECK-NEXT: movwlt r5, #1
; CHECK-NEXT: sub r0, r5, r7
; CHECK-NEXT: subs r0, r5, r0
; CHECK-NEXT: sbcs r0, r4, r1
; CHECK-NEXT: sbcs r0, lr, r2
; CHECK-NEXT: sbcs r0, r12, r3
; CHECK-NEXT: movwlt r6, #1
; CHECK-NEXT: sub r0, r6, r7
; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%1 = call i8 @llvm.scmp(i128 %x, i128 %y)
ret i8 %1
Expand Down
30 changes: 15 additions & 15 deletions llvm/test/CodeGen/ARM/ucmp.ll
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Expand Up @@ -58,23 +58,23 @@ define i8 @ucmp_8_128(i128 %x, i128 %y) nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: ldr r4, [sp, #24]
; CHECK-NEXT: mov r5, #0
; CHECK-NEXT: ldr r6, [sp, #28]
; CHECK-NEXT: subs r7, r0, r4
; CHECK-NEXT: ldr r12, [sp, #32]
; CHECK-NEXT: sbcs r7, r1, r6
; CHECK-NEXT: ldr lr, [sp, #36]
; CHECK-NEXT: sbcs r7, r2, r12
; CHECK-NEXT: sbcs r7, r3, lr
; CHECK-NEXT: ldr r5, [sp, #24]
; CHECK-NEXT: mov r6, #0
; CHECK-NEXT: ldr r4, [sp, #28]
; CHECK-NEXT: subs r7, r0, r5
; CHECK-NEXT: ldr lr, [sp, #32]
; CHECK-NEXT: sbcs r7, r1, r4
; CHECK-NEXT: ldr r12, [sp, #36]
; CHECK-NEXT: sbcs r7, r2, lr
; CHECK-NEXT: sbcs r7, r3, r12
; CHECK-NEXT: mov r7, #0
; CHECK-NEXT: movwlo r7, #1
; CHECK-NEXT: subs r0, r4, r0
; CHECK-NEXT: sbcs r0, r6, r1
; CHECK-NEXT: sbcs r0, r12, r2
; CHECK-NEXT: sbcs r0, lr, r3
; CHECK-NEXT: movwlo r5, #1
; CHECK-NEXT: sub r0, r5, r7
; CHECK-NEXT: subs r0, r5, r0
; CHECK-NEXT: sbcs r0, r4, r1
; CHECK-NEXT: sbcs r0, lr, r2
; CHECK-NEXT: sbcs r0, r12, r3
; CHECK-NEXT: movwlo r6, #1
; CHECK-NEXT: sub r0, r6, r7
; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%1 = call i8 @llvm.ucmp(i128 %x, i128 %y)
ret i8 %1
Expand Down
20 changes: 9 additions & 11 deletions llvm/test/CodeGen/PowerPC/memcmp.ll
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Expand Up @@ -6,12 +6,10 @@ define signext i32 @memcmp8(ptr nocapture readonly %buffer1, ptr nocapture reado
; CHECK: # %bb.0:
; CHECK-NEXT: ldbrx 3, 0, 3
; CHECK-NEXT: ldbrx 4, 0, 4
; CHECK-NEXT: cmpld 3, 4
; CHECK-NEXT: subc 3, 4, 3
; CHECK-NEXT: subfe 3, 4, 4
; CHECK-NEXT: li 4, -1
; CHECK-NEXT: neg 3, 3
; CHECK-NEXT: isellt 3, 4, 3
; CHECK-NEXT: subc 6, 4, 3
; CHECK-NEXT: sub 5, 3, 4
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: blr
%call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 8)
Expand All @@ -23,11 +21,11 @@ define signext i32 @memcmp4(ptr nocapture readonly %buffer1, ptr nocapture reado
; CHECK: # %bb.0:
; CHECK-NEXT: lwbrx 3, 0, 3
; CHECK-NEXT: lwbrx 4, 0, 4
; CHECK-NEXT: cmplw 3, 4
; CHECK-NEXT: sub 5, 4, 3
; CHECK-NEXT: li 3, -1
; CHECK-NEXT: rldicl 5, 5, 1, 63
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: subc 6, 4, 3
; CHECK-NEXT: sub 5, 3, 4
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: blr
%call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 4)
ret i32 %call
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/PowerPC/scmp.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -5,10 +5,10 @@ define i8 @scmp_8_8(i8 signext %x, i8 signext %y) nounwind {
; CHECK-LABEL: scmp_8_8:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpw 3, 4
; CHECK-NEXT: sub 5, 4, 3
; CHECK-NEXT: li 3, -1
; CHECK-NEXT: rldicl 5, 5, 1, 63
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: sub 3, 4, 3
; CHECK-NEXT: li 4, -1
; CHECK-NEXT: rldicl 3, 3, 1, 63
; CHECK-NEXT: isellt 3, 4, 3
; CHECK-NEXT: blr
%1 = call i8 @llvm.scmp(i8 %x, i8 %y)
ret i8 %1
Expand All @@ -18,10 +18,10 @@ define i8 @scmp_8_16(i16 signext %x, i16 signext %y) nounwind {
; CHECK-LABEL: scmp_8_16:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpw 3, 4
; CHECK-NEXT: sub 5, 4, 3
; CHECK-NEXT: li 3, -1
; CHECK-NEXT: rldicl 5, 5, 1, 63
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: sub 3, 4, 3
; CHECK-NEXT: li 4, -1
; CHECK-NEXT: rldicl 3, 3, 1, 63
; CHECK-NEXT: isellt 3, 4, 3
; CHECK-NEXT: blr
%1 = call i8 @llvm.scmp(i16 %x, i16 %y)
ret i8 %1
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