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[WIP][InstCombine] Add assume-based optimizations for equality and AMDGPU ballot patterns #160670

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[WIP][InstCombine] Add assume-based optimizations for equality and AMDGPU ballot patterns #160670

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ff9e194
[InstCombine] Optimize AMDGPU ballot + assume uniformity patterns
TejaX-Alaghari Sep 25, 2025
d86e492
[InstCombine] Add constant folding for AMDGPU ballot intrinsics
TejaX-Alaghari Sep 29, 2025
a711d52
[InstCombine] Implement generic assume-based uniformity optimization
TejaX-Alaghari Sep 29, 2025
b16fe02
[InstCombine] Add focused assume-based optimizations
TejaX-Alaghari Oct 2, 2025
40eeaff
Address @ssahasra's review feedback
TejaX-Alaghari Oct 5, 2025
08355f9
Address feedback on the location of the opt
TejaX-Alaghari Oct 7, 2025
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18 changes: 18 additions & 0 deletions llvm/lib/Transforms/Scalar/GVN.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Metadata.h"
#include "llvm/IR/Module.h"
Expand Down Expand Up @@ -2206,6 +2207,23 @@ bool GVNPass::processAssumeIntrinsic(AssumeInst *IntrinsicI) {
std::swap(CmpLHS, CmpRHS);
}

// Optimize AMDGPU ballot pattern: assume(ballot(cmp) == -1) or
// assume(ballot(cmp) == exec_mask). This implies cmp is true on all
// active lanes and hence can be replaced with true.
if (isa<IntrinsicInst>(CmpLHS) && isa<Constant>(CmpRHS)) {
auto *IntrCall = cast<IntrinsicInst>(CmpLHS);
// Check if CmpLHS is a ballot intrinsic
if (IntrCall->getIntrinsicID() ==
Intrinsic::AMDGCNIntrinsics::amdgcn_ballot) {
Value *BallotArg = IntrCall->getArgOperand(0);
if (BallotArg->getType()->isIntegerTy(1) &&
(match(CmpRHS, m_AllOnes()) || !isa<Constant>(CmpRHS))) {
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The second part here, !isa<Constant>(CmpRHS) ... is this meant to be execmask? What if it is simply a value that the programmer knows will match the current state of cmp across active threads? For example:

unsigned threadmask = foo(); // where a bit is 1 for whatever reason
if (divergent_condition) {
  cmp = bar();
  assume(ballot(cmp) == threadmask);
}

CmpLHS = BallotArg;
CmpRHS = ConstantInt::getTrue(BallotArg->getType());
}
}
}

// Handle degenerate case where we either haven't pruned a dead path or a
// removed a trivial assume yet.
if (isa<Constant>(CmpLHS) && isa<Constant>(CmpRHS))
Expand Down
29 changes: 29 additions & 0 deletions llvm/test/Transforms/GVN/assume-equal.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -387,6 +387,35 @@ define i8 @assume_ptr_eq_same_prov(ptr %p, i64 %x) {
ret i8 %v
}

; Test AMDGPU ballot pattern optimization
; assume(ballot(cmp) == -1) means cmp is true on all active lanes
; so uses of cmp can be replaced with true
define void @assume_ballot_uniform(i32 %x) {
; CHECK-LABEL: @assume_ballot_uniform(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 0
; CHECK-NEXT: [[BALLOT:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[CMP]])
; CHECK-NEXT: [[ALL:%.*]] = icmp eq i64 [[BALLOT]], -1
; CHECK-NEXT: call void @llvm.assume(i1 [[ALL]])
; CHECK-NEXT: br i1 true, label [[FOO:%.*]], label [[BAR:%.*]]
; CHECK: foo:
; CHECK-NEXT: ret void
; CHECK: bar:
; CHECK-NEXT: ret void
;
%cmp = icmp eq i32 %x, 0
%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)
%all = icmp eq i64 %ballot, -1
call void @llvm.assume(i1 %all)
br i1 %cmp, label %foo, label %bar

foo:
ret void

bar:
ret void
}

declare i64 @llvm.amdgcn.ballot.i64(i1)
declare noalias ptr @_Znwm(i64)
declare void @_ZN1AC1Ev(ptr)
declare void @llvm.assume(i1)
Expand Down