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[HIP][SPIRV] Use OPT_fembed_bitcode_EQ instead of the alias OPT_fembed_bitcode_marker #162258

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[HIP][SPIRV] Use OPT_fembed_bitcode_EQ instead of the alias OPT_fembed_bitcode_marker #162258

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f1d1f13
Pre-commit tests: [HIP][SPIRV] Use OPT_fembed_bitcode_EQ instead of t…
jmmartinez Oct 7, 2025
7678a3e
[HIP][SPIRV] Use OPT_fembed_bitcode_EQ instead of the alias OPT_fembe…
jmmartinez Oct 7, 2025
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2 changes: 1 addition & 1 deletion clang/lib/Driver/ToolChains/HIPAMD.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -259,7 +259,7 @@ void HIPAMDToolChain::addClangTargetOptions(
// For SPIR-V we embed the command-line into the generated binary, in order
// to retrieve it at JIT time and be able to do target specific compilation
// with options that match the user-supplied ones.
if (!DriverArgs.hasArg(options::OPT_fembed_bitcode_marker))
if (!DriverArgs.hasArg(options::OPT_fembed_bitcode_EQ))
CC1Args.push_back("-fembed-bitcode=marker");
// For SPIR-V we want to retain the pristine output of Clang CodeGen, since
// optimizations might lose structure / information that is necessary for
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18 changes: 18 additions & 0 deletions clang/test/Driver/hip-toolchain-no-rdc.hip
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Expand Up @@ -41,6 +41,18 @@
// RUN: %s -nogpuinc -nogpulib \
// RUN: 2>&1 | FileCheck -check-prefixes=AMDGCNSPIRV %s

// Only the first case where -fembed-bitcode-marker is used is relevant.
// The next 2 cases only verify that the user's will is respected.
// RUN: %clang -### --target=x86_64-linux-gnu \
// RUN: --offload-arch=amdgcnspirv --offload-arch=gfx900 -fembed-bitcode=all \
// RUN: %s -nogpuinc -nogpulib \
// RUN: 2>&1 | FileCheck -check-prefixes="AMDGCNSPIRV-EMBED,AMDGCNSPIRV-NOMARKER" %s

// RUN: %clang -### --target=x86_64-linux-gnu \
// RUN: --offload-arch=amdgcnspirv --offload-arch=gfx900 -fembed-bitcode=off \
// RUN: %s -nogpuinc -nogpulib \
// RUN: 2>&1 | FileCheck -check-prefixes=AMDGCNSPIRV-NOMARKER %s

//
// Compile device code in a.cu to code object for gfx803.
//
Expand Down Expand Up @@ -214,3 +226,9 @@
// AMDGCNSPIRV: {{".*clang-offload-bundler.*"}} "-type=o"
// AMDGCNSPIRV-SAME: "-targets={{.*}}hipv4-spirv64-amd-amdhsa--amdgcnspirv,hipv4-amdgcn-amd-amdhsa--gfx900"
// AMDGCNSPIRV-SAME: "-input=[[AMDGCNSPV_CO]]" "-input=[[GFX900_CO]]"

// Only check that no confliction options are passed
// AMDGCNSPIRV-NOMARKER-NOT: "-fembed-bitcode=marker"
// AMDGCNSPIRV-NOMARKER-NOT: "-fembed-bitcode-marker"
// AMDGCNSPIRV-EMBED: "-cc1" "-triple" "spirv64-amd-amdhsa" {{.*}}"-emit-llvm-bc" {{.*}} "-disable-llvm-passes" {{.*}} "-o" "[[AMDGCNSPV_FIRST_BC:.*bc]]"
// AMDGCNSPIRV-EMBED: "-cc1" "-triple" "spirv64-amd-amdhsa" {{.*}}"-emit-llvm-bc" {{.*}}"-fembed-bitcode=all"{{.*}} "-o" "[[AMDGCNSPV_BC:.*bc]]" "-x" "ir" "[[AMDGCNSPV_FIRST_BC]]"
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