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[AMDGPU] Use RegisterOperand instead of RegisterClass in MIMGNSAHelper #162911

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[AMDGPU] Use RegisterOperand instead of RegisterClass in MIMGNSAHelper #162911

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29 changes: 17 additions & 12 deletions llvm/lib/Target/AMDGPU/MIMGInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -260,8 +260,13 @@ class NSAHelper {
}

class MIMGNSAHelper<int num_addrs,
list<RegisterClass> addr_types=!listsplat(VGPR_32, num_addrs)>
: NSAHelper<> {
list<RegisterOperand> addr_types_in=[]>
: NSAHelper<> {
assert !ge(num_addrs, 0), "num_addrs must be > 0";
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Nit: !listsplat on line 267 should diagnose this error for you?

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Also the code says >= 0 but the comment says > 0.

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Nit: !listsplat on line 267 should diagnose this error for you?

... at least after #163152! If that works then maybe we can drop this hunk, and go back to giving addr_types a default of !listsplat(...)?

list<RegisterOperand> addr_types =
!if(!empty(addr_types_in), !listsplat(VGPROp_32, num_addrs),
addr_types_in);

list<string> AddrAsmNames = !foreach(i, !range(num_addrs), "vaddr" # i);
let AddrIns = !dag(ins, addr_types, AddrAsmNames);
let AddrAsm = "[$" # !interleave(AddrAsmNames, ", $") # "]";
Expand Down Expand Up @@ -358,7 +363,7 @@ class MIMG_gfx11<int op, dag outs, string dns = "">
// Base class for all NSA MIMG instructions.
// Note that 1-dword addresses always use non-NSA variants.
class MIMG_nsa_gfx11<int op, dag outs, int num_addrs, string dns="",
list<RegisterClass> addr_types=[],
list<RegisterOperand> addr_types=[],
RegisterOperand LastAddrRC = VGPROp_32>
: MIMG<outs, dns>, MIMGe_gfx11<op> {
let SubtargetPredicate = isGFX11Only;
Expand All @@ -378,7 +383,7 @@ class MIMG_nsa_gfx11<int op, dag outs, int num_addrs, string dns="",
}

class VIMAGE_gfx12<int op, dag outs, int num_addrs, string dns="",
list<RegisterClass> addr_types=[]>
list<RegisterOperand> addr_types=[]>
: VIMAGE<outs, dns>, VIMAGEe<op> {
let SubtargetPredicate = isGFX12Plus;
let AssemblerPredicate = isGFX12Plus;
Expand Down Expand Up @@ -1521,12 +1526,12 @@ class MIMG_IntersectRay_Helper<bit Is64, bit IsA16, bit isDual, bit isBVH8> {
int VAddrDwords = !srl(Size, 5);

int GFX11PlusNSAAddrs = !if(IsA16, 4, 5);
RegisterClass node_ptr_type = !if(Is64, VReg_64, VGPR_32);
list<RegisterClass> GFX11PlusAddrTypes =
!cond(isBVH8 : [node_ptr_type, VReg_64, VReg_96, VReg_96, VGPR_32],
isDual : [node_ptr_type, VReg_64, VReg_96, VReg_96, VReg_64],
IsA16 : [node_ptr_type, VGPR_32, VReg_96, VReg_96],
true : [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96]);
RegisterOperand node_ptr_type = !if(Is64, VGPROp_64, VGPROp_32);
list<RegisterOperand> GFX11PlusAddrTypes =
!cond(isBVH8 : [node_ptr_type, VGPROp_64, VGPROp_96, VGPROp_96, VGPROp_32],
isDual : [node_ptr_type, VGPROp_64, VGPROp_96, VGPROp_96, VGPROp_64],
IsA16 : [node_ptr_type, VGPROp_32, VGPROp_96, VGPROp_96],
true : [node_ptr_type, VGPROp_32, VGPROp_96, VGPROp_96, VGPROp_96]);
}

class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterOperand AddrRC>
Expand All @@ -1552,7 +1557,7 @@ class MIMG_IntersectRay_gfx11<mimgopc op, string opcode, RegisterOperand AddrRC>
}

class MIMG_IntersectRay_nsa_gfx11<mimgopc op, string opcode, int num_addrs,
list<RegisterClass> addr_types>
list<RegisterOperand> addr_types>
: MIMG_nsa_gfx11<op.GFX11, (outs VReg_128:$vdata), num_addrs, "GFX11",
addr_types> {
let InOperandList = !con(nsah.AddrIns, (ins SReg_128_XNULL:$srsrc, A16:$a16));
Expand All @@ -1561,7 +1566,7 @@ class MIMG_IntersectRay_nsa_gfx11<mimgopc op, string opcode, int num_addrs,

class VIMAGE_IntersectRay_gfx12<mimgopc op, string opcode, int num_addrs,
bit isDual, bit isBVH8,
list<RegisterClass> addr_types>
list<RegisterOperand> addr_types>
: VIMAGE_gfx12<op.GFX12, !if(!or(isDual, isBVH8),
(outs VReg_320:$vdata, VReg_96:$ray_origin_out,
VReg_96:$ray_dir_out),
Expand Down