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[Hexagon] Define V91 ISA and Processor versions in ELF flags #163631

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Merged
merged 2 commits into from
Oct 16, 2025
Merged

[Hexagon] Define V91 ISA and Processor versions in ELF flags #163631

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e14684f
[Hexagon] Define V91 ISA and Processor versions in ELF flags
quic-areg Oct 15, 2025
cd77335
update ELFYaml for V91
quic-areg Oct 16, 2025
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2 changes: 2 additions & 0 deletions llvm/include/llvm/BinaryFormat/ELF.h
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Original file line number Diff line number Diff line change
Expand Up @@ -647,6 +647,7 @@ enum {
EF_HEXAGON_ISA_V85 = 0x00000085, // Hexagon V85 ISA
EF_HEXAGON_ISA_V87 = 0x00000087, // Hexagon V87 ISA
EF_HEXAGON_ISA_V89 = 0x00000089, // Hexagon V89 ISA
EF_HEXAGON_ISA_V91 = 0x00000091, // Hexagon V91 ISA
EF_HEXAGON_ISA = 0x000003ff, // Hexagon V.. ISA

// Tiny core flag, bit[15]
Expand Down Expand Up @@ -680,6 +681,7 @@ enum {
EF_HEXAGON_MACH_V85 = EF_HEXAGON_ISA_V85, // Hexagon V85
EF_HEXAGON_MACH_V87 = EF_HEXAGON_ISA_V87, // Hexagon V87
EF_HEXAGON_MACH_V89 = EF_HEXAGON_ISA_V89, // Hexagon V89
EF_HEXAGON_MACH_V91 = EF_HEXAGON_ISA_V91, // Hexagon V91

EF_HEXAGON_MACH = 0x0000ffff, // Hexagon V..
};
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2 changes: 2 additions & 0 deletions llvm/lib/ObjectYAML/ELFYAML.cpp
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Expand Up @@ -507,6 +507,7 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
BCaseMask(EF_HEXAGON_MACH_V85, EF_HEXAGON_MACH);
BCaseMask(EF_HEXAGON_MACH_V87, EF_HEXAGON_MACH);
BCaseMask(EF_HEXAGON_MACH_V89, EF_HEXAGON_MACH);
BCaseMask(EF_HEXAGON_MACH_V91, EF_HEXAGON_MACH);
BCaseMask(EF_HEXAGON_ISA_V2, EF_HEXAGON_ISA);
BCaseMask(EF_HEXAGON_ISA_V3, EF_HEXAGON_ISA);
BCaseMask(EF_HEXAGON_ISA_V4, EF_HEXAGON_ISA);
Expand All @@ -530,6 +531,7 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
BCaseMask(EF_HEXAGON_ISA_V85, EF_HEXAGON_ISA);
BCaseMask(EF_HEXAGON_ISA_V87, EF_HEXAGON_ISA);
BCaseMask(EF_HEXAGON_ISA_V89, EF_HEXAGON_ISA);
BCaseMask(EF_HEXAGON_ISA_V91, EF_HEXAGON_ISA);
break;
case ELF::EM_AVR:
BCaseMask(EF_AVR_ARCH_AVR1, EF_AVR_ARCH_MASK);
Expand Down