[PowerPC] Add Implementation and test for new eTCE instructions

[lei137]

Add implementation and encoding tests for:

• tlbiep
• tlbsyncio
• ptesyncio

[llvmbot]

@llvm/pr-subscribers-backend-powerpc

Author: Lei Huang (lei137)

Changes

Add implementation and encoding tests for:

• tlbiep
• tlbsyncio
• ptesyncio

---

Full diff: https://github.com/llvm/llvm-project/pull/164002.diff

5 Files Affected:

• (modified) llvm/lib/Target/PowerPC/PPCInstrFormats.td (+27)
• (modified) llvm/lib/Target/PowerPC/PPCInstrFuture.td (+24)
• (modified) llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt (+9)
• (modified) llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt (+9)
• (modified) llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s (+12)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index fba1c6609dba0..13e00e67d6be6 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -850,6 +850,33 @@ class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
   let Inst{31}    = 0;
 }
 
+class XForm_RSB5_UIMM2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                              string asmstr, list<dag> pattern>
+    : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+
+  bits<5> RS;
+  bits<5> RB;
+  bits<2> RIC;
+
+  let Pattern = pattern;
+
+  let Inst{6...10} = RS;
+  let Inst{12...13} = RIC;
+  let Inst{16...20} = RB;
+  let Inst{21...30} = xo;
+}
+
+class XForm_RSB5_UIMM2_2UIMM1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                              string asmstr, list<dag> pattern>
+    : XForm_RSB5_UIMM2<opcode, xo, OOL, IOL, asmstr, pattern> {
+
+  bits<1> PRS;
+  bits<1> R;
+
+  let Inst{14} = PRS;
+  let Inst{15} = R;
+}
+
 class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
                          dag OOL, dag IOL, string asmstr, InstrItinClass itin,
                          list<dag> pattern>
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 1aefea1a1c498..9cc820447b51d 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -11,6 +11,15 @@
 //
 //===----------------------------------------------------------------------===//
 
+class XForm_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+                list<dag> pattern> : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+  bits<5> RS;
+
+  let Pattern = pattern;
+  let Inst{6...10} = RS;
+  let Inst{21...30} = xo;
+}
+
 class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
                       string asmstr, list<dag> pattern>
     : I<opcode, OOL, IOL, asmstr, NoItinerary> {
@@ -294,6 +303,21 @@ let Predicates = [IsISAFuture] in {
   defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
                                  (ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
                                  "$RT, $L, $RA, $RB", []>;
+  def TLBSYNCIO
+      : XForm_RS5<31, 564, (outs), (ins g8rc:$RS), "tlbsyncio $RS", []>;
+  def PTESYNCIO
+      : XForm_RS5<31, 596, (outs), (ins g8rc:$RS), "ptesyncio $RS", []>;
+  def TLBIEP : XForm_RSB5_UIMM2_2UIMM1<31, 50, (outs),
+                                       (ins gprc:$RB, gprc:$RS, u2imm:$RIC,
+                                           u1imm:$PRS, u1imm:$R),
+                                       "tlbiep $RB, $RS, $RIC, $PRS, $R", []>;
+  let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
+    def TLBIEP8
+        : XForm_RSB5_UIMM2_2UIMM1<31, 50, (outs),
+                                  (ins g8rc:$RB, g8rc:$RS, u2imm:$RIC,
+                                      u1imm:$PRS, u1imm:$R),
+                                  "tlbiep $RB, $RS, $RIC, $PRS, $R", []>;
+  }
 }
 
 let Predicates = [HasVSX, IsISAFuture] in {
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index cdfc8ce9e0ca5..5400cf6996c4c 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -7,6 +7,15 @@
 # RUN: llvm-mc --disassemble %s -triple powerpc-unknown-aix-gnu \
 # RUN:   -mcpu=future | FileCheck %s
 
+#CHECK: tlbiep 8, 10, 2, 1, 0
+0x7d 0x4a 0x40 0x64
+
+#CHECK: tlbsyncio 15
+0x7d 0xe0 0x04 0x68
+
+#CHECK: ptesyncio 15
+0x7d 0xe0 0x04 0xa8
+
 #CHECK: dmxxextfdmr512 2, 34, 1, 0
 0xf0 0x82 0x17 0x12
 
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index f7e314fc819e4..5260fd19f940e 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -1,6 +1,15 @@
 # RUN: llvm-mc --disassemble %s -triple powerpc64le-unknown-unknown \
 # RUN:   -mcpu=future | FileCheck %s
 
+#CHECK: tlbiep 8, 10, 2, 1, 0
+0x64 0x40 0x4a 0x7d
+
+#CHECK: tlbsyncio 15
+0x68 0x04 0xe0 0x7d
+
+#CHECK: ptesyncio 15
+0xa8 0x04 0xe0 0x7d
+
 #CHECK: dmxxextfdmr512 2, 34, 1, 0
 0x12 0x17 0x82 0xf0
 
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index 29fedd7c20646..27524f93a28fe 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -5,6 +5,18 @@
 # RUN: llvm-mc -triple powerpc-unknown-aix-gnu --show-encoding %s | \
 # RUN:   FileCheck -check-prefix=CHECK-BE %s
 
+#CHECK-BE: tlbiep 8, 10, 2, 1, 0          # encoding: [0x7d,0x4a,0x40,0x64]
+#CHECK-LE: tlbiep 8, 10, 2, 1, 0          # encoding: [0x64,0x40,0x4a,0x7d]
+           tlbiep 8, 10, 2, 1, 0
+
+# CHECK-BE: tlbsyncio 15                  # encoding: [0x7d,0xe0,0x04,0x68]
+# CHECK-LE: tlbsyncio 15                  # encoding: [0x68,0x04,0xe0,0x7d]
+            tlbsyncio 15
+
+# CHECK-BE: ptesyncio 15                  # encoding: [0x7d,0xe0,0x04,0xa8]
+# CHECK-LE: ptesyncio 15                  # encoding: [0xa8,0x04,0xe0,0x7d]
+            ptesyncio 15
+
 # CHECK-BE: dmxxextfdmr512 2, 34, 1, 0    # encoding: [0xf0,0x82,0x17,0x12]
 # CHECK-LE: dmxxextfdmr512 2, 34, 1, 0    # encoding: [0x12,0x17,0x82,0xf0]
             dmxxextfdmr512 2, 34, 1, 0