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[PowerPC] Add Implementation and test for new eTCE instructions #164002

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9748091
Add implementation and encoding tests for tlbsyncio & ptesyncio
lei137 Oct 7, 2025
17be99c
add class introduced in update for ISA3.0 tlbie
lei137 Oct 9, 2025
bf89a68
add encoding and tests for tlbiep
lei137 Oct 9, 2025
401c450
update test format
lei137 Oct 17, 2025
313aecc
update class inheritance as intermediate is needed for next patch
lei137 Oct 17, 2025
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27 changes: 27 additions & 0 deletions llvm/lib/Target/PowerPC/PPCInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -850,6 +850,33 @@ class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = 0;
}

class XForm_RSB5_UIMM2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, NoItinerary> {

bits<5> RS;
bits<5> RB;
bits<2> RIC;

let Pattern = pattern;

let Inst{6...10} = RS;
let Inst{12...13} = RIC;
let Inst{16...20} = RB;
let Inst{21...30} = xo;
}

class XForm_RSB5_UIMM2_2UIMM1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
: XForm_RSB5_UIMM2<opcode, xo, OOL, IOL, asmstr, pattern> {

bits<1> PRS;
bits<1> R;

let Inst{14} = PRS;
let Inst{15} = R;
}

class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
dag OOL, dag IOL, string asmstr, InstrItinClass itin,
list<dag> pattern>
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24 changes: 24 additions & 0 deletions llvm/lib/Target/PowerPC/PPCInstrFuture.td
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Expand Up @@ -11,6 +11,15 @@
//
//===----------------------------------------------------------------------===//

class XForm_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
list<dag> pattern> : I<opcode, OOL, IOL, asmstr, NoItinerary> {
bits<5> RS;

let Pattern = pattern;
let Inst{6...10} = RS;
let Inst{21...30} = xo;
}

class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, NoItinerary> {
Expand Down Expand Up @@ -294,6 +303,21 @@ let Predicates = [IsISAFuture] in {
defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
(ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
"$RT, $L, $RA, $RB", []>;
def TLBSYNCIO
: XForm_RS5<31, 564, (outs), (ins g8rc:$RS), "tlbsyncio $RS", []>;
def PTESYNCIO
: XForm_RS5<31, 596, (outs), (ins g8rc:$RS), "ptesyncio $RS", []>;
def TLBIEP : XForm_RSB5_UIMM2_2UIMM1<31, 50, (outs),
(ins gprc:$RB, gprc:$RS, u2imm:$RIC,
u1imm:$PRS, u1imm:$R),
"tlbiep $RB, $RS, $RIC, $PRS, $R", []>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def TLBIEP8
: XForm_RSB5_UIMM2_2UIMM1<31, 50, (outs),
(ins g8rc:$RB, g8rc:$RS, u2imm:$RIC,
u1imm:$PRS, u1imm:$R),
"tlbiep $RB, $RS, $RIC, $PRS, $R", []>;
}
}

let Predicates = [HasVSX, IsISAFuture] in {
Expand Down
9 changes: 9 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
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Expand Up @@ -7,6 +7,15 @@
# RUN: llvm-mc --disassemble %s -triple powerpc-unknown-aix-gnu \
# RUN: -mcpu=future | FileCheck %s

#CHECK: tlbiep 8, 10, 2, 1, 0
0x7d 0x4a 0x40 0x64

#CHECK: tlbsyncio 15
0x7d 0xe0 0x04 0x68

#CHECK: ptesyncio 15
0x7d 0xe0 0x04 0xa8

#CHECK: dmxxextfdmr512 2, 34, 1, 0
0xf0 0x82 0x17 0x12

Expand Down
9 changes: 9 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
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Original file line number Diff line number Diff line change
@@ -1,6 +1,15 @@
# RUN: llvm-mc --disassemble %s -triple powerpc64le-unknown-unknown \
# RUN: -mcpu=future | FileCheck %s

#CHECK: tlbiep 8, 10, 2, 1, 0
0x64 0x40 0x4a 0x7d

#CHECK: tlbsyncio 15
0x68 0x04 0xe0 0x7d

#CHECK: ptesyncio 15
0xa8 0x04 0xe0 0x7d

#CHECK: dmxxextfdmr512 2, 34, 1, 0
0x12 0x17 0x82 0xf0

Expand Down
12 changes: 12 additions & 0 deletions llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
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Expand Up @@ -5,6 +5,18 @@
# RUN: llvm-mc -triple powerpc-unknown-aix-gnu --show-encoding %s | \
# RUN: FileCheck -check-prefix=CHECK-BE %s

#CHECK-BE: tlbiep 8, 10, 2, 1, 0 # encoding: [0x7d,0x4a,0x40,0x64]
#CHECK-LE: tlbiep 8, 10, 2, 1, 0 # encoding: [0x64,0x40,0x4a,0x7d]
tlbiep 8, 10, 2, 1, 0

# CHECK-BE: tlbsyncio 15 # encoding: [0x7d,0xe0,0x04,0x68]
# CHECK-LE: tlbsyncio 15 # encoding: [0x68,0x04,0xe0,0x7d]
tlbsyncio 15

# CHECK-BE: ptesyncio 15 # encoding: [0x7d,0xe0,0x04,0xa8]
# CHECK-LE: ptesyncio 15 # encoding: [0xa8,0x04,0xe0,0x7d]
ptesyncio 15

# CHECK-BE: dmxxextfdmr512 2, 34, 1, 0 # encoding: [0xf0,0x82,0x17,0x12]
# CHECK-LE: dmxxextfdmr512 2, 34, 1, 0 # encoding: [0x12,0x17,0x82,0xf0]
dmxxextfdmr512 2, 34, 1, 0
Expand Down